Audio: STM32 ADC: extended driver to STM32H7 family
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Silvano Seva
parent
3d04759e8d
commit
1a15f793f3
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@ -1,5 +1,5 @@
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Copyright (C) 2023 - 2024 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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@ -19,17 +19,36 @@
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***************************************************************************/
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#include <kernel/scheduler/scheduler.h>
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#include <core/cache_cortexMx.h>
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#include <interfaces/delays.h>
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#include <peripherals/gpio.h>
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#include <DmaStream.hpp>
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#include <Timer.hpp>
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#include <hwconfig.h>
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#include <miosix.h>
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#include <errno.h>
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#include "stm32_adc.h"
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#if defined(STM32H743xx)
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#include <Lptim.hpp>
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typedef Lptim timebase_type;
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#define TimebaseCh1 Lptim(LPTIM3_BASE, 168000000)
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#define TimebaseCh2 Lptim(LPTIM3_BASE, 168000000)
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#define TimebaseCh3 Lptim(LPTIM3_BASE, 168000000)
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#else
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#include <Timer.hpp>
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typedef Timer timebase_type;
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#define TimebaseCh1 Timer(TIM2_BASE)
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#define TimebaseCh2 Timer(TIM2_BASE)
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#define TimebaseCh3 Timer(TIM2_BASE)
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#endif
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struct AdcPeriph
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{
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ADC_TypeDef *adc;
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StreamHandler *stream;
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Timer tim;
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timebase_type tim;
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};
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using Dma2_Stream0 = DmaStream< DMA2_BASE, 0, 0, 2 >; // DMA 2, Stream 2, channel 0, high priority (ADC1)
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@ -44,9 +63,9 @@ static struct streamCtx *AdcContext[3];
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static constexpr AdcPeriph periph[] =
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{
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{(ADC_TypeDef *) ADC1_BASE, &Dma2_Stream0_hdl, Timer(TIM2_BASE)},
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{(ADC_TypeDef *) ADC2_BASE, &Dma2_Stream2_hdl, Timer(TIM2_BASE)},
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{(ADC_TypeDef *) ADC3_BASE, &Dma2_Stream1_hdl, Timer(TIM2_BASE)},
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{(ADC_TypeDef *) ADC1_BASE, &Dma2_Stream0_hdl, TimebaseCh1},
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{(ADC_TypeDef *) ADC2_BASE, &Dma2_Stream2_hdl, TimebaseCh2},
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{(ADC_TypeDef *) ADC3_BASE, &Dma2_Stream1_hdl, TimebaseCh3},
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};
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@ -56,8 +75,16 @@ static constexpr AdcPeriph periph[] =
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*/
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static void stopTransfer(const uint8_t instNum)
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{
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ADC_TypeDef *adc = periph[instNum].adc;
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#ifdef STM32H743xx
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adc->CR |= ADC_CR_ADSTP;
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while((adc->CR & ADC_CR_ADSTP) != 0) ;
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#else
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adc->CR2 &= ~ADC_CR2_ADON;
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#endif
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periph[instNum].tim.stop();
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periph[instNum].adc->CR2 &= ~ADC_CR2_ADON;
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AdcContext[instNum]->running = 0;
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}
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@ -117,16 +144,37 @@ void stm32adc_init(const uint8_t instance)
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// Enable peripherals
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switch(instance)
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{
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case 0:
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case STM32_ADC_ADC1:
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#ifdef STM32H743xx
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RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN;
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ADC12_COMMON->CCR = ADC_CCR_CKMODE_1
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| ADC_CCR_CKMODE_0;
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DMAMUX1_Channel8->CCR = 9;
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#else
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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#endif
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break;
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case 1:
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case STM32_ADC_ADC2:
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#ifdef STM32H743xx
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RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN;
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ADC12_COMMON->CCR = ADC_CCR_CKMODE_1
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| ADC_CCR_CKMODE_0;
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DMAMUX1_Channel10->CCR = 10;
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#else
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RCC->APB2ENR |= RCC_APB2ENR_ADC2EN;
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#endif
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break;
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case 2:
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case STM32_ADC_ADC3:
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#ifdef STM32H743xx
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RCC->AHB4ENR |= RCC_AHB4ENR_ADC3EN;
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ADC3_COMMON->CCR = ADC_CCR_CKMODE_1
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| ADC_CCR_CKMODE_0;
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DMAMUX1_Channel9->CCR = 115;
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#else
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RCC->APB2ENR |= RCC_APB2ENR_ADC3EN;
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#endif
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break;
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}
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@ -134,24 +182,41 @@ void stm32adc_init(const uint8_t instance)
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* Use TIM2 as trigger source for all the ADCs.
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* TODO: change this with a dedicated timer for each ADC.
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*/
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#ifdef STM32H743xx
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RCC->APB4ENR |= RCC_APB4ENR_LPTIM3EN;
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RCC->D3CCIPR |= RCC_D3CCIPR_LPTIM345SEL_0;
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uint32_t adcTrig = 20 << ADC_CFGR_EXTSEL_Pos; // lptim3_out as trig. source
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#else
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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uint32_t adcTrig = ADC_CR2_EXTSEL_1 // 0b0110 TIM2_TRGO trig. source
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| ADC_CR2_EXTSEL_2;
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ADC->CCR |= ADC_CCR_ADCPRE_0;
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uint32_t adcTrig = ADC_CR2_EXTSEL_2 // 0b0110 TIM2_TRGO trig. source
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| ADC_CR2_EXTSEL_1;
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#endif
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__DSB();
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/*
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* ADC configuration.
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*
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* ADC clock is APB2 frequency divided by 4, giving 21MHz.
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* Channel sample time set to 84 cycles, total conversion time is 100
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* cycles: this leads to a maximum sampling frequency of 210kHz.
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* Convert one channel only, no overrun interrupt, 12-bit resolution,
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* no analog watchdog, discontinuous mode, no end of conversion interrupts.
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*/
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ADC_TypeDef *adc = periph[instance].adc;
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ADC->CCR |= ADC_CCR_ADCPRE_0;
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#ifdef STM32H743xx
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adc->CR = ADC_CR_ADVREGEN
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| ADC_CR_BOOST_1
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| ADC_CR_BOOST_0;
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while((adc->ISR & ADC_ISR_LDORDY) == 0) ;
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adc->ISR = ADC_ISR_ADRDY; // Clear the ADRDY flag
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adc->CR |= ADC_CR_ADEN;
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while((adc->ISR & ADC_ISR_ADRDY) != 0) ;
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adc->SMPR2 = 0x36DB6DB6;
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adc->SMPR1 = 0x36DB6DB6;
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adc->SQR1 = 0; // Convert one channel
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adc->CFGR |= ADC_CFGR_DISCEN
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| ADC_CFGR_EXTEN_0 // Trigger on rising edge
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| adcTrig // Trigger source
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| ADC_CFGR_RES_1 // 12-bit resolution
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| ADC_CFGR_DMNGT_1 // Continuous DMA requests
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| ADC_CFGR_DMNGT_0; // Enable DMA data transfer
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#else
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adc->SMPR2 = ADC_SMPR2_SMP2_2
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| ADC_SMPR2_SMP1_2;
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adc->SQR1 = 0; // Convert one channel
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@ -160,6 +225,7 @@ void stm32adc_init(const uint8_t instance)
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| adcTrig // Trigger source
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| ADC_CR2_DDS // Continuous DMA requests
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| ADC_CR2_DMA; // Enable DMA data transfer
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#endif
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// Register end-of-transfer callbacks
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periph[instance].stream->setEndTransferCallback(std::bind(stopTransfer, instance));
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@ -178,7 +244,11 @@ void stm32adc_terminate()
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}
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// TODO: turn off peripherals
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#ifdef STM32H743xx
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RCC->APB1LENR &= ~RCC_APB1LENR_TIM2EN;
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#else
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
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#endif
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__DSB();
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}
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@ -198,8 +268,17 @@ static int stm32adc_start(const uint8_t instance, const void *config, struct str
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AdcContext[instance] = ctx;
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// Set conversion channel and enable the ADC
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periph[instance].adc->SQR3 = (uint32_t) config;
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periph[instance].adc->CR2 |= ADC_CR2_ADON;
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ADC_TypeDef *adc = periph[instance].adc;
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#ifdef STM32H743xx
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uint32_t channel = (uint32_t) config;
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adc->SQR1 = channel << ADC_SQR1_SQ1_Pos;
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adc->PCSEL = 1 << channel;
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adc->CR |= ADC_CR_ADSTART;
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#else
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adc->SQR3 = (uint32_t) config;
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adc->CR2 |= ADC_CR2_ADON;
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#endif
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// Start DMA stream
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bool circ = false;
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@ -220,15 +299,18 @@ static int stm32adc_data(struct streamCtx *ctx, stream_sample_t **buf)
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{
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AdcPeriph *p = reinterpret_cast< AdcPeriph * >(ctx->priv);
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// Default case: linear mode
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*buf = ctx->buffer;
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int size = ctx->bufSize;
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if(ctx->bufMode == BUF_CIRC_DOUBLE)
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{
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*buf = reinterpret_cast< stream_sample_t *>(p->stream->idleBuf());
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return ctx->bufSize/2;
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size = ctx->bufSize/2;
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}
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// Linear mode: return the full buffer
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*buf = ctx->buffer;
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return ctx->bufSize;
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miosix::markBufferAfterDmaRead(*buf, size*sizeof(int16_t));
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return size;
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}
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static int stm32adc_sync(struct streamCtx *ctx, uint8_t dirty)
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@ -1,5 +1,5 @@
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Copyright (C) 2023 - 2024 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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@ -23,7 +23,6 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include <stm32f4xx.h>
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#include <interfaces/audio.h>
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#ifdef __cplusplus
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