diff --git a/openrtx/src/graphics.c b/openrtx/src/graphics.c index 6f4818cd..123cfc72 100644 --- a/openrtx/src/graphics.c +++ b/openrtx/src/graphics.c @@ -163,21 +163,24 @@ inline void gfx_setPixel(point_t pos, color_t color) #ifdef PIX_FMT_RGB565 // Blend old pixel value and new one - if (color.alpha < 255) { + if (color.alpha < 255) + { uint8_t alpha = color.alpha; rgb565_t new_pixel = _true2highColor(color); - uint16_t raw_pixel = *((uint16_t *)buf + pos.x + pos.y*SCREEN_WIDTH); - rgb565_t old_pixel = *((rgb565_t*) &raw_pixel); + rgb565_t old_pixel = buf[pos.x + pos.y*SCREEN_WIDTH]; rgb565_t pixel = {((255-alpha)*old_pixel.b+alpha*new_pixel.b)/255, ((255-alpha)*old_pixel.g+alpha*new_pixel.g)/255, ((255-alpha)*old_pixel.r+alpha*new_pixel.r)/255}; buf[pos.x + pos.y*SCREEN_WIDTH] = pixel; - } else { + } + else + { buf[pos.x + pos.y*SCREEN_WIDTH] = _true2highColor(color); } #elif defined PIX_FMT_BW // Ignore more than half transparent pixels - if (color.alpha >= 128) { + if (color.alpha >= 128) + { uint16_t cell = (pos.x + pos.y*SCREEN_WIDTH) / 8; uint16_t elem = (pos.x + pos.y*SCREEN_WIDTH) % 8; buf[cell] &= ~(1 << elem); @@ -243,19 +246,18 @@ void gfx_drawVLine(uint16_t x, uint16_t width, color_t color) * @param text: the input text * @param length: the length of the input text, used for boundary checking */ -static inline uint16_t get_line_size(GFXfont f, - const char *text, - uint16_t length) { +static inline uint16_t get_line_size(GFXfont f, const char *text, uint16_t length) +{ uint16_t line_size = 0; - for(unsigned i = 0; - i < length && text[i] != '\n' && text[i] != '\r'; - i++) { + for(unsigned i = 0; i < length && text[i] != '\n' && text[i] != '\r'; i++) + { GFXglyph glyph = f.glyph[text[i] - f.first]; if (line_size + glyph.xAdvance < SCREEN_WIDTH) line_size += glyph.xAdvance; else break; } + return line_size; } @@ -264,9 +266,9 @@ static inline uint16_t get_line_size(GFXfont f, * @param alinment: enum representing the text alignment * @param line_size: the size of the current text line in pixels */ -static inline uint16_t get_reset_x(textAlign_t alignment, - uint16_t line_size, - uint16_t startx) { +static inline uint16_t get_reset_x(textAlign_t alignment, uint16_t line_size, + uint16_t startx) +{ switch(alignment) { case TEXT_ALIGN_LEFT: @@ -276,10 +278,13 @@ static inline uint16_t get_reset_x(textAlign_t alignment, case TEXT_ALIGN_RIGHT: return SCREEN_WIDTH - line_size - startx; } + return 0; } -point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t alignment, color_t color) { +point_t gfx_print(point_t start, const char *text, fontSize_t size, + textAlign_t alignment, color_t color) +{ GFXfont f = fonts[size]; @@ -289,13 +294,14 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t uint16_t line_size = get_line_size(f, text, len); uint16_t reset_x = get_reset_x(alignment, line_size, start.x); start.x = reset_x; - + // Save initial start.y value to calculate vertical size uint16_t saved_start_y = start.y; uint16_t line_h = 0; /* For each char in the string */ - for(unsigned i = 0; i < len; i++) { + for(unsigned i = 0; i < len; i++) + { char c = text[i]; GFXglyph glyph = f.glyph[c - f.first]; uint8_t *bitmap = f.bitmap; @@ -308,17 +314,21 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t line_h = h; // Handle newline and carriage return - if (c == '\n') { + if (c == '\n') + { start.x = reset_x; start.y += f.yAdvance; continue; - } else if (c == '\r') { + } + else if (c == '\r') + { start.x = reset_x; continue; } // Handle wrap around - if (start.x + glyph.xAdvance > SCREEN_WIDTH) { + if (start.x + glyph.xAdvance > SCREEN_WIDTH) + { // Compute size of the first row in pixels line_size = get_line_size(f, text, len); start.x = reset_x = get_reset_x(alignment, line_size, start.x); @@ -326,12 +336,17 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t } // Draw bitmap - for (yy = 0; yy < h; yy++) { - for (xx = 0; xx < w; xx++) { - if (!(bit++ & 7)) { + for (yy = 0; yy < h; yy++) + { + for (xx = 0; xx < w; xx++) + { + if (!(bit++ & 7)) + { bits = bitmap[bo++]; } - if (bits & 0x80) { + + if (bits & 0x80) + { if (start.y + yo + yy < SCREEN_HEIGHT && start.x + xo + xx < SCREEN_WIDTH && start.y + yo + yy > 0 && @@ -342,9 +357,11 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t } } + bits <<= 1; } } + start.x += glyph.xAdvance; } // Calculate text size @@ -355,7 +372,8 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t } // Print an error message to the center of the screen, surronded by a red (when possible) box -void gfx_printError(const char *text, fontSize_t size) { +void gfx_printError(const char *text, fontSize_t size) +{ // 3 px box padding uint16_t box_padding = 16; color_t white = {255, 255, 255, 255}; @@ -382,8 +400,8 @@ void gfx_printError(const char *text, fontSize_t size) { * * ******* * | * * ******* ** | * * ******* ** | <-- Height (px) - * * ******* * | - * * * | + * * ******* * | + * * * | * **************** | * * __________________ @@ -394,7 +412,9 @@ void gfx_printError(const char *text, fontSize_t size) { * Width (px) * */ -void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, float percentage) { +void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, + float percentage) +{ color_t white = {255, 255, 255, 255}; color_t black = {0, 0, 0 , 255}; @@ -421,7 +441,8 @@ void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, float perce // Draw the battery fill point_t fill_start = {start.x + 2, start.y + 2}; - gfx_drawRect(fill_start, (int)(((float)(width - 4)) * percentage), height - 4, bat_color, true); + gfx_drawRect(fill_start, (int)(((float)(width - 4)) * percentage), + height - 4, bat_color, true); // Round corners point_t top_left = start; @@ -459,13 +480,16 @@ void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, float perce * Width (px) * */ -void gfx_drawSmeter(point_t start, uint16_t width, uint16_t height, float rssi, float squelch, color_t color) { +void gfx_drawSmeter(point_t start, uint16_t width, uint16_t height, float rssi, + float squelch, color_t color) +{ color_t white = {255, 255, 255, 255}; color_t yellow = {250, 180, 19 , 255}; color_t red = {255, 0, 0 , 255}; // S-level dots - for(int i = 0; i < 11; i++) { + for(int i = 0; i < 11; i++) + { color_t color = (i % 3 == 0) ? yellow : white; color = (i > 9) ? red : color; point_t pixel_pos = {i * (width - 1) / 11, start.y}; @@ -473,6 +497,7 @@ void gfx_drawSmeter(point_t start, uint16_t width, uint16_t height, float rssi, pixel_pos.y += height; gfx_setPixel(pixel_pos, color); } + point_t pixel_pos = {width - 1, start.y}; gfx_setPixel(pixel_pos, red); pixel_pos.y += height; diff --git a/openrtx/src/ui/ui_main.c b/openrtx/src/ui/ui_main.c index ea445119..d39a7f2b 100644 --- a/openrtx/src/ui/ui_main.c +++ b/openrtx/src/ui/ui_main.c @@ -67,7 +67,7 @@ void _ui_drawMainTop() void _ui_drawZoneChannel() { char zone_buf[20] = ""; - char channel_buf[20] = ""; + char channel_buf[25] = ""; if(!last_state.zone_enabled) snprintf(zone_buf, sizeof(zone_buf), "zone: %.13s", "All channels"); else @@ -83,7 +83,7 @@ void _ui_drawZoneChannel() void _ui_drawFrequency() { // Print big numbers frequency - char freq_buf[10] = ""; + char freq_buf[15] = ""; snprintf(freq_buf, sizeof(freq_buf), "%03lu.%05lu", (unsigned long)last_state.channel.rx_frequency/1000000, (unsigned long)last_state.channel.rx_frequency%1000000/10); diff --git a/platform/drivers/NVM/nvmem_GDx.c b/platform/drivers/NVM/nvmem_GDx.c index f126ca65..7460313a 100644 --- a/platform/drivers/NVM/nvmem_GDx.c +++ b/platform/drivers/NVM/nvmem_GDx.c @@ -241,15 +241,21 @@ void nvm_loadHwInfo(hwInfo_t *info) int nvm_readChannelData(channel_t *channel, uint16_t pos) { + (void) channel; + (void) pos; return -1; } int nvm_readZoneData(zone_t *zone, uint16_t pos) { + (void) zone; + (void) pos; return -1; } int nvm_readContactData(contact_t *contact, uint16_t pos) { + (void) contact; + (void) pos; return -1; } diff --git a/platform/mcu/STM32F4xx/drivers/usb/usb_core.c b/platform/mcu/STM32F4xx/drivers/usb/usb_core.c index 2521449e..97e2860b 100644 --- a/platform/mcu/STM32F4xx/drivers/usb/usb_core.c +++ b/platform/mcu/STM32F4xx/drivers/usb/usb_core.c @@ -16,8 +16,8 @@ * * http://www.st.com/software_license_agreement_liberty_v2 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. @@ -43,7 +43,7 @@ struct __attribute__((packed, aligned(1))) T_UINT32_READ { uint32_t v; }; * @{ */ -/** @defgroup USB_CORE +/** @defgroup USB_CORE * @brief This file includes the USB-OTG Core Layer * @{ */ @@ -51,49 +51,49 @@ struct __attribute__((packed, aligned(1))) T_UINT32_READ { uint32_t v; }; /** @defgroup USB_CORE_Private_Defines * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_CORE_Private_TypesDefinitions * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_CORE_Private_Macros * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_CORE_Private_Variables * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_CORE_Private_FunctionPrototypes * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_CORE_Private_Functions * @{ -*/ +*/ /** * @brief USB_OTG_EnableCommonInt @@ -104,7 +104,7 @@ struct __attribute__((packed, aligned(1))) T_UINT32_READ { uint32_t v; }; static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_GINTMSK_TypeDef int_mask; - + int_mask.d32 = 0; /* Clear any pending USB_OTG Interrupts */ #ifndef USE_OTG_MODE @@ -114,8 +114,8 @@ static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); /* Enable the interrupts in the INTMSK */ int_mask.b.wkupintr = 1; - int_mask.b.usbsuspend = 1; - + int_mask.b.usbsuspend = 1; + #ifdef USE_OTG_MODE int_mask.b.otgintr = 1; int_mask.b.sessreqintr = 1; @@ -134,7 +134,7 @@ static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) USB_OTG_STS status = USB_OTG_OK; __IO USB_OTG_GRSTCTL_TypeDef greset; uint32_t count = 0; - + greset.d32 = 0; /* Wait for AHB master IDLE state. */ do @@ -166,7 +166,7 @@ static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) } /** -* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated +* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated * with the EP * @param pdev : Selected device * @param src : source pointer @@ -174,9 +174,9 @@ static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) * @param bytes : No. of bytes * @retval USB_OTG_STS : status */ -USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *src, - uint8_t ch_ep_num, +USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, + uint8_t *src, + uint8_t ch_ep_num, uint16_t len) { USB_OTG_STS status = USB_OTG_OK; @@ -184,7 +184,7 @@ USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, { uint32_t count32b= 0 , i= 0; __IO uint32_t *fifo; - + count32b = (len + 3) / 4; fifo = pdev->regs.DFIFO[ch_ep_num]; for (i = 0; i < count32b; i++, src+=4) @@ -203,42 +203,42 @@ USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, * @param bytes : No. of bytes * @retval None */ -void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dest, +void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, + uint8_t *dest, uint16_t len) { uint32_t i=0; uint32_t count32b = (len + 3) / 4; - + __IO uint32_t *fifo = pdev->regs.DFIFO[0]; - + for ( i = 0; i < count32b; i++, dest += 4 ) { __UNALIGNED_UINT32_WRITE(dest, USB_OTG_READ_REG32(fifo)); - + } return ((void *)dest); } /** -* @brief USB_OTG_SelectCore +* @brief USB_OTG_SelectCore * Initialize core registers address. * @param pdev : Selected device * @param coreID : USB OTG Core ID * @retval USB_OTG_STS : status */ -USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, +USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID) { uint32_t i , baseAddress = 0; USB_OTG_STS status = USB_OTG_OK; - + pdev->cfg.dma_enable = 0; - + /* at startup the core is in FS mode */ pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - + pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; + /* initialize device cfg following its address */ if (coreID == USB_OTG_FS_CORE_ID) { @@ -247,51 +247,51 @@ USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, pdev->cfg.host_channels = 8 ; pdev->cfg.dev_endpoints = 4 ; pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - -#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif + pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; + +#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED + pdev->cfg.Sof_output = 1; +#endif + +#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT + pdev->cfg.low_power = 1; +#endif } else if (coreID == USB_OTG_HS_CORE_ID) { baseAddress = USB_OTG_HS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_HS_CORE_ID; + pdev->cfg.coreID = USB_OTG_HS_CORE_ID; pdev->cfg.host_channels = 12 ; pdev->cfg.dev_endpoints = 6 ; pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ - + #ifdef USB_OTG_ULPI_PHY_ENABLED pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; -#else +#else #ifdef USB_OTG_EMBEDDED_PHY_ENABLED pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; -#endif -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pdev->cfg.dma_enable = 1; #endif - -#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - +#endif + +#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED + pdev->cfg.dma_enable = 1; +#endif + +#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED + pdev->cfg.Sof_output = 1; +#endif + +#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT + pdev->cfg.low_power = 1; +#endif + } - + pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ USB_OTG_CORE_GLOBAL_REGS_OFFSET); pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ USB_OTG_DEV_GLOBAL_REG_OFFSET); - + for (i = 0; i < pdev->cfg.dev_endpoints; i++) { pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ @@ -304,7 +304,7 @@ USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ USB_OTG_HOST_GLOBAL_REG_OFFSET); pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); - + for (i = 0; i < pdev->cfg.host_channels; i++) { pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ @@ -317,7 +317,7 @@ USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, (i * USB_OTG_DATA_FIFO_SIZE)); } pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); - + return status; } @@ -335,57 +335,57 @@ USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) USB_OTG_GUSBCFG_TypeDef usbcfg; USB_OTG_GCCFG_TypeDef gccfg; USB_OTG_GAHBCFG_TypeDef ahbcfg; - + usbcfg.d32 = 0; gccfg.d32 = 0; ahbcfg.d32 = 0; - - - + + + if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) { gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); gccfg.b.pwdn = 0; - + if (pdev->cfg.Sof_output) { - gccfg.b.sofouten = 1; + gccfg.b.sofouten = 1; } USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - + /* Init The ULPI Interface */ usbcfg.d32 = 0; usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - + usbcfg.b.physel = 0; /* HS Interface */ #ifdef USB_OTG_INTERNAL_VBUS_ENABLED usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ #else -#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED +#ifdef USB_OTG_EXTERNAL_VBUS_ENABLED usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ #endif -#endif - usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ - +#endif + usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ + usbcfg.b.ulpi_fsls = 0; usbcfg.b.ulpi_clk_sus_m = 0; USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - + /* Reset after a PHY select */ USB_OTG_CoreReset(pdev); - + if(pdev->cfg.dma_enable == 1) { - + ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ ahbcfg.b.dmaenable = 1; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } + + } } else /* FS interface (embedded Phy) */ { - + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; usbcfg.b.physel = 1; /* FS Interface */ USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); @@ -394,30 +394,30 @@ USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) /* Deactivate the power down*/ gccfg.d32 = 0; gccfg.b.pwdn = 1; - + gccfg.b.vbussensingA = 1 ; - gccfg.b.vbussensingB = 1 ; + gccfg.b.vbussensingB = 1 ; #ifndef VBUS_SENSING_ENABLED - gccfg.b.disablevbussensing = 1; -#endif - + gccfg.b.disablevbussensing = 1; +#endif + if(pdev->cfg.Sof_output) { - gccfg.b.sofouten = 1; + gccfg.b.sofouten = 1; } - + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); USB_OTG_BSP_mDelay(20); } /* case the HS core is working in FS mode */ if(pdev->cfg.dma_enable == 1) { - + ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ ahbcfg.b.dmaenable = 1; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - + } /* initialize OTG features */ #ifdef USE_OTG_MODE @@ -439,7 +439,7 @@ USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_STS status = USB_OTG_OK; USB_OTG_GAHBCFG_TypeDef ahbcfg; - + ahbcfg.d32 = 0; ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); @@ -474,7 +474,7 @@ USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) { USB_OTG_STS status = USB_OTG_OK; __IO USB_OTG_GRSTCTL_TypeDef greset; - + uint32_t count = 0; greset.d32 = 0; greset.b.txfflsh = 1; @@ -505,7 +505,7 @@ USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) USB_OTG_STS status = USB_OTG_OK; __IO USB_OTG_GRSTCTL_TypeDef greset; uint32_t count = 0; - + greset.d32 = 0; greset.b.rxfflsh = 1; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); @@ -534,12 +534,12 @@ USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) { USB_OTG_STS status = USB_OTG_OK; USB_OTG_GUSBCFG_TypeDef usbcfg; - + usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - + usbcfg.b.force_host = 0; usbcfg.b.force_dev = 0; - + if ( mode == HOST_MODE) { usbcfg.b.force_host = 1; @@ -548,7 +548,7 @@ USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) { usbcfg.b.force_dev = 1; } - + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); USB_OTG_BSP_mDelay(50); return status; @@ -622,44 +622,44 @@ USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_STS status = USB_OTG_OK; USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef ptxfifosize; + USB_OTG_FSIZ_TypeDef ptxfifosize; USB_OTG_HCFG_TypeDef hcfg; - + #ifdef USE_OTG_MODE USB_OTG_OTGCTL_TypeDef gotgctl; #endif - + uint32_t i = 0; - - nptxfifosize.d32 = 0; + + nptxfifosize.d32 = 0; ptxfifosize.d32 = 0; #ifdef USE_OTG_MODE gotgctl.d32 = 0; #endif hcfg.d32 = 0; - - + + /* configure charge pump IO */ USB_OTG_BSP_ConfigVBUS(pdev); - + /* Restart the Phy Clock */ USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - + /* Initialize Host Configuration Register */ if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); + USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ); } else { - USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); + USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); } USB_OTG_ResetPort(pdev); - + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); hcfg.b.fslssupp = 0; USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); - + /* Configure data FIFO sizes */ /* Rx FIFO */ #ifdef USB_OTG_FS_CORE @@ -667,41 +667,41 @@ USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) { /* set Rx FIFO size */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; + nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; + nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - + ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); } #endif -#ifdef USB_OTG_HS_CORE +#ifdef USB_OTG_HS_CORE if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) { /* set Rx FIFO size */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; + nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; + nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - + ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); } -#endif - +#endif + #ifdef USE_OTG_MODE /* Clear Host Set HNP Enable in the USB_OTG Control Register */ gotgctl.b.hstsethnpen = 1; USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); #endif - + /* Make sure the FIFOs are flushed. */ USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ USB_OTG_FlushRxFifo(pdev); - - + + /* Clear all pending HC Interrupts */ for (i = 0; i < pdev->cfg.host_channels; i++) { @@ -711,18 +711,18 @@ USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) #ifndef USE_OTG_MODE USB_OTG_DriveVbus(pdev, 1); #endif - + USB_OTG_EnableHostInt(pdev); return status; } /** -* @brief USB_OTG_IsEvenFrame +* @brief USB_OTG_IsEvenFrame * This function returns the frame number for sof packet * @param pdev : Selected device * @retval Frame number */ -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) +uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) { return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); } @@ -736,12 +736,12 @@ uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) { USB_OTG_HPRT0_TypeDef hprt0; - + hprt0.d32 = 0; - + /* enable disable the external charge pump */ USB_OTG_BSP_DriveVBUS(pdev, state); - + /* Turn on the Host port power. */ hprt0.d32 = USB_OTG_ReadHPRT0(pdev); if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) @@ -754,7 +754,7 @@ void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) hprt0.b.prtpwr = 0; USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); } - + USB_OTG_BSP_mDelay(200); } /** @@ -769,28 +769,28 @@ USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) intmsk.d32 = 0; /* Disable all interrupts. */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); - + /* Clear any pending interrupts. */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - + /* Enable the common interrupts */ USB_OTG_EnableCommonInt(pdev); - + if (pdev->cfg.dma_enable == 0) - { + { intmsk.b.rxstsqlvl = 1; - } + } intmsk.b.portintr = 1; intmsk.b.hcintr = 1; - intmsk.b.disconnect = 1; - intmsk.b.sofintr = 1; - intmsk.b.incomplisoout = 1; + intmsk.b.disconnect = 1; + intmsk.b.sofintr = 1; + intmsk.b.incomplisoout = 1; USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); return status; } /** -* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the +* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type * @param pdev : Selected device * @param freq : clock frequency @@ -799,7 +799,7 @@ USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) { USB_OTG_HCFG_TypeDef hcfg; - + hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); hcfg.b.fslspclksel = freq; USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); @@ -814,7 +814,7 @@ void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_HPRT0_TypeDef hprt0; - + hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); hprt0.b.prtena = 0; hprt0.b.prtconndet = 0; @@ -845,14 +845,14 @@ uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_HPRT0_TypeDef hprt0; - + hprt0.d32 = USB_OTG_ReadHPRT0(pdev); hprt0.b.prtrst = 1; USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); USB_OTG_BSP_mDelay (10); /* See Note #1 */ hprt0.b.prtrst = 0; USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (20); + USB_OTG_BSP_mDelay (20); return 1; } @@ -871,25 +871,25 @@ USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) USB_OTG_GINTMSK_TypeDef gintmsk; USB_OTG_HCCHAR_TypeDef hcchar; USB_OTG_HCINTn_TypeDef hcint; - - + + gintmsk.d32 = 0; hcintmsk.d32 = 0; hcchar.d32 = 0; - + /* Clear old interrupt conditions for this host channel. */ hcint.d32 = 0xFFFFFFFF; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); - + /* Enable channel interrupts required for this transfer. */ hcintmsk.d32 = 0; - + if (pdev->cfg.dma_enable == 1) { hcintmsk.b.ahberr = 1; } - - switch (pdev->host.hc[hc_num].ep_type) + + switch (pdev->host.hc[hc_num].ep_type) { case EP_TYPE_CTRL: case EP_TYPE_BULK: @@ -897,15 +897,15 @@ USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) hcintmsk.b.stall = 1; hcintmsk.b.xacterr = 1; hcintmsk.b.datatglerr = 1; - hcintmsk.b.nak = 1; - if (pdev->host.hc[hc_num].ep_is_in) + hcintmsk.b.nak = 1; + if (pdev->host.hc[hc_num].ep_is_in) { hcintmsk.b.bblerr = 1; - } - else + } + else { hcintmsk.b.nyet = 1; - if (pdev->host.hc[hc_num].do_ping) + if (pdev->host.hc[hc_num].do_ping) { hcintmsk.b.ack = 1; } @@ -918,38 +918,38 @@ USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) hcintmsk.b.xacterr = 1; hcintmsk.b.datatglerr = 1; hcintmsk.b.frmovrun = 1; - - if (pdev->host.hc[hc_num].ep_is_in) + + if (pdev->host.hc[hc_num].ep_is_in) { hcintmsk.b.bblerr = 1; } - + break; case EP_TYPE_ISOC: hcintmsk.b.xfercompl = 1; hcintmsk.b.frmovrun = 1; hcintmsk.b.ack = 1; - - if (pdev->host.hc[hc_num].ep_is_in) + + if (pdev->host.hc[hc_num].ep_is_in) { hcintmsk.b.xacterr = 1; hcintmsk.b.bblerr = 1; } break; } - - + + USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32); - - + + /* Enable the top level host channel interrupt. */ intr_enable = (1 << hc_num); USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); - + /* Make sure host channel interrupts are enabled. */ gintmsk.b.hcintr = 1; USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); - + /* Program the HCCHAR register */ hcchar.d32 = 0; hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; @@ -978,25 +978,25 @@ USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) USB_OTG_STS status = USB_OTG_OK; USB_OTG_HCCHAR_TypeDef hcchar; USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; + USB_OTG_HNPTXSTS_TypeDef hnptxsts; + USB_OTG_HPTXSTS_TypeDef hptxsts; USB_OTG_GINTMSK_TypeDef intmsk; - uint16_t len_words = 0; - + uint16_t len_words = 0; + uint16_t num_packets; uint16_t max_hc_pkt_count; - + max_hc_pkt_count = 256; hctsiz.d32 = 0; hcchar.d32 = 0; intmsk.d32 = 0; - + /* Compute the expected number of packets associated to the transfer */ if (pdev->host.hc[hc_num].xfer_len > 0) { num_packets = (pdev->host.hc[hc_num].xfer_len + \ pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; - + if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; @@ -1018,43 +1018,43 @@ USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) hctsiz.b.pktcnt = num_packets; hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - + if (pdev->cfg.dma_enable == 1) { USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); } - - + + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); - + /* Set host channel enable */ hcchar.b.chen = 1; hcchar.b.chdis = 0; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - + if (pdev->cfg.dma_enable == 0) /* Slave mode */ - { - if((pdev->host.hc[hc_num].ep_is_in == 0) && + { + if((pdev->host.hc[hc_num].ep_is_in == 0) && (pdev->host.hc[hc_num].xfer_len > 0)) { - switch(pdev->host.hc[hc_num].ep_type) + switch(pdev->host.hc[hc_num].ep_type) { /* Non periodic transfer */ case EP_TYPE_CTRL: case EP_TYPE_BULK: - + hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - + /* check if there is enough space in FIFO space */ if(len_words > hnptxsts.b.nptxfspcavail) { /* need to process data in nptxfempty interrupt */ intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); } - + break; /* Periodic transfer */ case EP_TYPE_INTR: @@ -1066,17 +1066,17 @@ USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) { /* need to process data in ptxfempty interrupt */ intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); + USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); } break; - + default: break; } - + /* Write packet into the Tx FIFO. */ - USB_OTG_WritePacket(pdev, - pdev->host.hc[hc_num].xfer_buff , + USB_OTG_WritePacket(pdev, + pdev->host.hc[hc_num].xfer_buff , hc_num, pdev->host.hc[hc_num].xfer_len); } } @@ -1096,13 +1096,13 @@ USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) USB_OTG_HNPTXSTS_TypeDef nptxsts; USB_OTG_HPTXSTS_TypeDef hptxsts; USB_OTG_HCCHAR_TypeDef hcchar; - + nptxsts.d32 = 0; hptxsts.d32 = 0; hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); hcchar.b.chen = 1; hcchar.b.chdis = 1; - + /* Check for space in the request queue to issue the halt. */ if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) { @@ -1133,18 +1133,18 @@ USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) { USB_OTG_STS status = USB_OTG_OK; USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - + USB_OTG_HCTSIZn_TypeDef hctsiz; + hctsiz.d32 = 0; hctsiz.b.dopng = 1; hctsiz.b.pktcnt = 1; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - + hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); hcchar.b.chen = 1; hcchar.b.chdis = 0; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; + return status; } /** @@ -1156,11 +1156,11 @@ void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_HCCHAR_TypeDef hcchar; uint32_t i; - + USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); /* Flush out any leftover queued requests. */ - + for (i = 0; i < pdev->cfg.host_channels; i++) { hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); @@ -1169,17 +1169,17 @@ void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) hcchar.b.epdir = 0; USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); } - + /* Flush the FIFO */ USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); + USB_OTG_FlushTxFifo(pdev , 0x10 ); } #endif #ifdef USE_DEVICE_MODE /* PCD Core Layer */ /** -* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register +* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. * @param pdev : Selected device * @retval : None @@ -1187,7 +1187,7 @@ void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) { USB_OTG_DCFG_TypeDef dcfg; - + dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); dcfg.b.devspd = speed; USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); @@ -1195,7 +1195,7 @@ void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) /** -* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers +* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers * for device mode * @param pdev : Selected device * @retval USB_OTG_STS : status @@ -1209,50 +1209,50 @@ USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) USB_OTG_FSIZ_TypeDef nptxfifosize; USB_OTG_FSIZ_TypeDef txfifosize; USB_OTG_DIEPMSK_TypeDef msk; - USB_OTG_DTHRCTL_TypeDef dthrctl; - + USB_OTG_DTHRCTL_TypeDef dthrctl; + depctl.d32 = 0; dcfg.d32 = 0; nptxfifosize.d32 = 0; txfifosize.d32 = 0; msk.d32 = 0; - + /* Restart the Phy Clock */ USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); /* Device configuration register */ dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); - + #ifdef USB_OTG_FS_CORE if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) - { - + { + /* Set Full speed phy */ USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); - + /* set Rx FIFO size */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - + /* EP0 TX*/ nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - + + /* EP1 TX*/ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; txfifosize.b.depth = TX1_FIFO_FS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - + + /* EP2 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX2_FIFO_FS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ + + + /* EP3 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX3_FIFO_FS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); @@ -1261,9 +1261,9 @@ USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) #ifdef USB_OTG_HS_CORE if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) { - + /* Set High speed phy */ - + if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) { USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); @@ -1272,45 +1272,45 @@ USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) { USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); } - + /* set Rx FIFO size */ USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - + /* EP0 TX*/ nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - + + /* EP1 TX*/ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; txfifosize.b.depth = TX1_FIFO_HS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - + + /* EP2 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX2_FIFO_HS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ + + + /* EP3 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX3_FIFO_HS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - + /* EP4 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX4_FIFO_HS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); - - - /* EP5 TX*/ + + + /* EP5 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX5_FIFO_HS_SIZE; USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); } -#endif +#endif /* Flush the FIFOs */ USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ USB_OTG_FlushRxFifo(pdev); @@ -1319,7 +1319,7 @@ USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - + for (i = 0; i < pdev->cfg.dev_endpoints; i++) { depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); @@ -1358,7 +1358,7 @@ USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) msk.d32 = 0; msk.b.txfifoundrn = 1; USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); - + if (pdev->cfg.dma_enable == 1) { dthrctl.d32 = 0; @@ -1367,7 +1367,7 @@ USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) dthrctl.b.tx_thr_len = 64; dthrctl.b.rx_thr_en = 1; dthrctl.b.rx_thr_len = 64; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); + USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); } USB_OTG_EnableDevInt(pdev); return status; @@ -1383,35 +1383,35 @@ USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_STS status = USB_OTG_OK; USB_OTG_GINTMSK_TypeDef intmsk; - + intmsk.d32 = 0; - + /* Disable all interrupts. */ USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); /* Clear any pending interrupts */ USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF); /* Enable the common interrupts */ USB_OTG_EnableCommonInt(pdev); - + if (pdev->cfg.dma_enable == 0) { intmsk.b.rxstsqlvl = 1; } - + /* Enable interrupts matching to the Device mode ONLY */ intmsk.b.usbsuspend = 1; intmsk.b.usbreset = 1; intmsk.b.enumdone = 1; intmsk.b.inepintr = 1; intmsk.b.outepintr = 1; - intmsk.b.sofintr = 1; - - intmsk.b.incomplisoin = 1; - intmsk.b.incomplisoout = 1; + intmsk.b.sofintr = 1; + + intmsk.b.incomplisoin = 1; + intmsk.b.incomplisoout = 1; #ifdef VBUS_SENSING_ENABLED - intmsk.b.sessreqintr = 1; - intmsk.b.otgintr = 1; -#endif + intmsk.b.sessreqintr = 1; + intmsk.b.otgintr = 1; +#endif USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); return status; } @@ -1427,10 +1427,10 @@ enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) { USB_OTG_DSTS_TypeDef dsts; enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; - - + + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - + switch (dsts.b.enumspd) { case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: @@ -1440,12 +1440,12 @@ enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) case DSTS_ENUMSPD_FS_PHY_48MHZ: speed = USB_SPEED_FULL; break; - + case DSTS_ENUMSPD_LS_PHY_6MHZ: speed = USB_SPEED_LOW; break; } - + return speed; } /** @@ -1460,7 +1460,7 @@ USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) USB_OTG_DSTS_TypeDef dsts; USB_OTG_DEPCTL_TypeDef diepctl; USB_OTG_DCTL_TypeDef dctl; - + dctl.d32 = 0; /* Read the Device Status and Endpoint 0 Control registers */ dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); @@ -1495,8 +1495,8 @@ USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_DEPCTL_TypeDef depctl; USB_OTG_DAINT_TypeDef daintmsk; __IO uint32_t *addr; - - + + depctl.d32 = 0; daintmsk.d32 = 0; /* Read DEPCTLn register */ @@ -1529,7 +1529,7 @@ USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); } else -#endif +#endif USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); return status; } @@ -1546,9 +1546,9 @@ USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_DEPCTL_TypeDef depctl; USB_OTG_DAINT_TypeDef daintmsk; __IO uint32_t *addr; - + depctl.d32 = 0; - daintmsk.d32 = 0; + daintmsk.d32 = 0; /* Read DEPCTLn register */ if (ep->is_in == 1) { @@ -1563,21 +1563,21 @@ USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) depctl.b.usbactep = 0; USB_OTG_WRITE_REG32(addr, depctl.d32); /* Disable the Interrupt for this EP */ - + #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) { USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); } else -#endif +#endif USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); return status; } /** -* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and +* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and * starts the xfer * @param pdev : Selected device * @retval USB_OTG_STS : status @@ -1587,9 +1587,9 @@ USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_STS status = USB_OTG_OK; USB_OTG_DEPCTL_TypeDef depctl; USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - USB_OTG_DSTS_TypeDef dsts; - uint32_t fifoemptymsk = 0; - + USB_OTG_DSTS_TypeDef dsts; + uint32_t fifoemptymsk = 0; + depctl.d32 = 0; deptsiz.d32 = 0; /* IN endpoint */ @@ -1612,14 +1612,14 @@ USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) */ deptsiz.b.xfersize = ep->xfer_len; deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; - + if (ep->type == EP_TYPE_ISOC) { deptsiz.b.mc = 1; - } + } } USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); - + if (pdev->cfg.dma_enable == 1) { USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); @@ -1636,12 +1636,12 @@ USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) } } } - - + + if (ep->type == EP_TYPE_ISOC) { dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - + if (((dsts.b.soffn)&0x1) == 0) { depctl.b.setd1pid = 1; @@ -1650,17 +1650,17 @@ USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) { depctl.b.setd0pid = 1; } - } - + } + /* EP enable, IN data in FIFO */ depctl.b.cnak = 1; depctl.b.epena = 1; USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); - + if (ep->type == EP_TYPE_ISOC) { - USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); - } + USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); + } } else { @@ -1682,12 +1682,12 @@ USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; } USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - + if (pdev->cfg.dma_enable == 1) { USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); } - + if (ep->type == EP_TYPE_ISOC) { if (ep->even_odd_frame) @@ -1709,7 +1709,7 @@ USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) /** -* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and +* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and * starts the xfer * @param pdev : Selected device * @retval USB_OTG_STS : status @@ -1721,7 +1721,7 @@ USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; USB_OTG_INEPREGS *in_regs; uint32_t fifoemptymsk = 0; - + depctl.d32 = 0; deptsiz.d32 = 0; /* IN endpoint */ @@ -1735,7 +1735,7 @@ USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) { deptsiz.b.xfersize = 0; deptsiz.b.pktcnt = 1; - + } else { @@ -1751,19 +1751,19 @@ USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) deptsiz.b.pktcnt = 1; } USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); - + if (pdev->cfg.dma_enable == 1) { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); + USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); } - + /* EP enable, IN data in FIFO */ depctl.b.cnak = 1; depctl.b.epena = 1; USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); - - - + + + if (pdev->cfg.dma_enable == 0) { /* Enable the Tx FIFO Empty Interrupt for this EP */ @@ -1804,7 +1804,7 @@ USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) depctl.b.cnak = 1; depctl.b.epena = 1; USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); - + } return status; } @@ -1820,7 +1820,7 @@ USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_STS status = USB_OTG_OK; USB_OTG_DEPCTL_TypeDef depctl; __IO uint32_t *depctl_addr; - + depctl.d32 = 0; if (ep->is_in == 1) { @@ -1856,9 +1856,9 @@ USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) USB_OTG_STS status = USB_OTG_OK; USB_OTG_DEPCTL_TypeDef depctl; __IO uint32_t *depctl_addr; - + depctl.d32 = 0; - + if (ep->is_in == 1) { depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); @@ -1934,14 +1934,14 @@ void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) doeptsize0.b.pktcnt = 1; doeptsize0.b.xfersize = 8 * 3; USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); - + if (pdev->cfg.dma_enable == 1) { USB_OTG_DEPCTL_TypeDef doepctl; doepctl.d32 = 0; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, + USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, (uint32_t)&pdev->dev.setup_packet); - + /* EP enable */ doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); doepctl.b.epena = 1; @@ -1957,12 +1957,12 @@ void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) */ void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) { - + USB_OTG_DCTL_TypeDef dctl; USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - if (pdev->dev.DevRemoteWakeup) + USB_OTG_PCGCCTL_TypeDef power; + + if (pdev->dev.DevRemoteWakeup) { dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); if(dsts.b.suspsts == 1) @@ -1970,11 +1970,13 @@ void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) if(pdev->cfg.low_power) { /* un-gate USB Core clock */ + #pragma GCC diagnostic ignored "-Wstrict-aliasing" power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); power.b.gatehclk = 0; power.b.stoppclk = 0; USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } + #pragma GCC diagnostic pop + } /* active Remote wakeup signaling */ dctl.d32 = 0; dctl.b.rmtwkupsig = 1; @@ -1995,20 +1997,22 @@ void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) { if(pdev->cfg.low_power) { - + USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - + USB_OTG_PCGCCTL_TypeDef power; + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - + if(dsts.b.suspsts == 1) { /* un-gate USB Core clock */ + #pragma GCC diagnostic ignored "-Wstrict-aliasing" power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); power.b.gatehclk = 0; power.b.stoppclk = 0; USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - + #pragma GCC diagnostic pop + } } } @@ -2021,23 +2025,23 @@ void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) { uint32_t i; - + pdev->dev.device_status = 1; - + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) { USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); } - + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - + USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); + /* Flush the FIFO */ USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); + USB_OTG_FlushTxFifo(pdev , 0x10 ); } /** @@ -2051,34 +2055,34 @@ uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) { USB_OTG_DEPCTL_TypeDef depctl; __IO uint32_t *depctl_addr; - uint32_t Status = 0; - + uint32_t Status = 0; + depctl.d32 = 0; if (ep->is_in == 1) { depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (depctl.b.stall == 1) + + if (depctl.b.stall == 1) Status = USB_OTG_EP_TX_STALL; else if (depctl.b.naksts == 1) Status = USB_OTG_EP_TX_NAK; - else - Status = USB_OTG_EP_TX_VALID; - + else + Status = USB_OTG_EP_TX_VALID; + } else { depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - if (depctl.b.stall == 1) + if (depctl.b.stall == 1) Status = USB_OTG_EP_RX_STALL; else if (depctl.b.naksts == 1) Status = USB_OTG_EP_RX_NAK; - else - Status = USB_OTG_EP_RX_VALID; - } - + else + Status = USB_OTG_EP_RX_VALID; + } + /* Return the current status */ return Status; } @@ -2094,16 +2098,16 @@ void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t { USB_OTG_DEPCTL_TypeDef depctl; __IO uint32_t *depctl_addr; - + depctl.d32 = 0; - + /* Process for IN endpoint */ if (ep->is_in == 1) { depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_TX_STALL) + + if (Status == USB_OTG_EP_TX_STALL) { USB_OTG_EPSetStall(pdev, ep); return; } @@ -2112,23 +2116,23 @@ void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t else if (Status == USB_OTG_EP_TX_VALID) { if (depctl.b.stall == 1) - { + { ep->even_odd_frame = 0; USB_OTG_EPClearStall(pdev, ep); return; - } + } depctl.b.cnak = 1; - depctl.b.usbactep = 1; + depctl.b.usbactep = 1; depctl.b.epena = 1; } else if (Status == USB_OTG_EP_TX_DIS) depctl.b.usbactep = 0; - } + } else /* Process for OUT endpoint */ { depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - + depctl.d32 = USB_OTG_READ_REG32(depctl_addr); + if (Status == USB_OTG_EP_RX_STALL) { depctl.b.stall = 1; } @@ -2137,32 +2141,32 @@ void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t else if (Status == USB_OTG_EP_RX_VALID) { if (depctl.b.stall == 1) - { + { ep->even_odd_frame = 0; USB_OTG_EPClearStall(pdev, ep); return; - } + } depctl.b.cnak = 1; - depctl.b.usbactep = 1; + depctl.b.usbactep = 1; depctl.b.epena = 1; } else if (Status == USB_OTG_EP_RX_DIS) { - depctl.b.usbactep = 0; + depctl.b.usbactep = 0; } } - - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); + + USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); } #endif /** * @} -*/ +*/ /** * @} -*/ +*/ /** * @} diff --git a/platform/mcu/STM32F4xx/drivers/usb/usb_dcd_int.c b/platform/mcu/STM32F4xx/drivers/usb/usb_dcd_int.c index a22da136..1bff5af2 100644 --- a/platform/mcu/STM32F4xx/drivers/usb/usb_dcd_int.c +++ b/platform/mcu/STM32F4xx/drivers/usb/usb_dcd_int.c @@ -16,8 +16,8 @@ * * http://www.st.com/software_license_agreement_liberty_v2 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. @@ -31,7 +31,7 @@ * @{ */ -/** @defgroup USB_DCD_INT +/** @defgroup USB_DCD_INT * @brief This file contains the interrupt subroutines for the Device mode. * @{ */ @@ -39,40 +39,40 @@ /** @defgroup USB_DCD_INT_Private_Defines * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_DCD_INT_Private_TypesDefinitions * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_DCD_INT_Private_Macros * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_DCD_INT_Private_Variables * @{ -*/ +*/ /** * @} -*/ +*/ /** @defgroup USB_DCD_INT_Private_FunctionPrototypes * @{ -*/ +*/ /* static functions */ static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); @@ -98,15 +98,15 @@ static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); /** * @} -*/ +*/ /** @defgroup USB_DCD_INT_Private_Functions * @{ -*/ +*/ -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED /** * @brief USBD_OTG_EP1OUT_ISR_Handler * handles all USB Interrupts @@ -115,13 +115,13 @@ static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); */ uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) { - + USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - + USB_OTG_DEPXFRSIZ_TypeDef deptsiz; + doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); - + /* Transfer complete */ if ( doepint.b.xfercompl ) { @@ -133,13 +133,13 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) /*ToDo : handle more than one single MPS size packet */ pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \ deptsiz.b.xfersize; - } + } /* Inform upper layer: data ready */ /* RX COMPLETE */ USBD_DCD_INT_fops->DataOutStage(pdev , 1); - + } - + /* Endpoint disable */ if ( doepint.b.epdisabled ) { @@ -158,15 +158,15 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) */ uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) { - + USB_OTG_DIEPINTn_TypeDef diepint; uint32_t fifoemptymsk, msk, emp; - + msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); msk |= ((emp >> 1 ) & 0x1) << 7; - diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; - + diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; + if ( diepint.b.xfercompl ) { fifoemptymsk = 0x1 << 1; @@ -178,7 +178,7 @@ uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) if ( diepint.b.epdisabled ) { CLEAR_IN_EP_INTR(1, epdisabled); - } + } if ( diepint.b.timeout ) { CLEAR_IN_EP_INTR(1, timeout); @@ -210,7 +210,7 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) { USB_OTG_GINTSTS_TypeDef gintr_status; uint32_t retval = 0; - + if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ { gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); @@ -218,32 +218,32 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) { return 0; } - + if (gintr_status.b.outepintr) { retval |= DCD_HandleOutEP_ISR(pdev); - } - + } + if (gintr_status.b.inepint) { retval |= DCD_HandleInEP_ISR(pdev); } - + if (gintr_status.b.modemismatch) { USB_OTG_GINTSTS_TypeDef gintsts; - + /* Clear interrupt */ gintsts.d32 = 0; gintsts.b.modemismatch = 1; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); } - + if (gintr_status.b.wkupintr) { retval |= DCD_HandleResume_ISR(pdev); } - + if (gintr_status.b.usbsuspend) { retval |= DCD_HandleUSBSuspend_ISR(pdev); @@ -251,25 +251,25 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) if (gintr_status.b.sofintr) { retval |= DCD_HandleSof_ISR(pdev); - + } - + if (gintr_status.b.rxstsqlvl) { retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); - + } - + if (gintr_status.b.usbreset) { retval |= DCD_HandleUsbReset_ISR(pdev); - + } if (gintr_status.b.enumdone) { retval |= DCD_HandleEnumDone_ISR(pdev); } - + if (gintr_status.b.incomplisoin) { retval |= DCD_IsoINIncomplete_ISR(pdev); @@ -278,7 +278,7 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) if (gintr_status.b.incomplisoout) { retval |= DCD_IsoOUTIncomplete_ISR(pdev); - } + } #ifdef VBUS_SENSING_ENABLED if (gintr_status.b.sessreqintr) { @@ -288,8 +288,8 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) if (gintr_status.b.otgintr) { retval |= DCD_OTG_ISR(pdev); - } -#endif + } +#endif } return retval; } @@ -303,13 +303,13 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) */ static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) { - USB_OTG_GINTSTS_TypeDef gintsts; + USB_OTG_GINTSTS_TypeDef gintsts; USBD_DCD_INT_fops->DevConnected (pdev); /* Clear interrupt */ gintsts.d32 = 0; gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); + USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); return 1; } @@ -326,13 +326,13 @@ static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) USB_OTG_GOTGINT_TypeDef gotgint; gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - + if (gotgint.b.sesenddet) { USBD_DCD_INT_fops->DevDisconnected (pdev); } /* Clear OTG interrupt */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); return 1; } #endif @@ -348,24 +348,26 @@ static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) USB_OTG_GINTSTS_TypeDef gintsts; USB_OTG_DCTL_TypeDef devctl; USB_OTG_PCGCCTL_TypeDef power; - + if(pdev->cfg.low_power) { /* un-gate USB Core clock */ + #pragma GCC diagnostic ignored "-Wstrict-aliasing" power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); power.b.gatehclk = 0; power.b.stoppclk = 0; USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); + #pragma GCC diagnostic pop } - + /* Clear the Remote Wake-up Signaling */ devctl.d32 = 0; devctl.b.rmtwkupsig = 1; USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); - + /* Inform upper layer by the Resume Event */ USBD_DCD_INT_fops->Resume (pdev); - + /* Clear interrupt */ gintsts.d32 = 0; gintsts.b.wkupintr = 1; @@ -385,29 +387,29 @@ static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) USB_OTG_PCGCCTL_TypeDef power; USB_OTG_DSTS_TypeDef dsts; __IO uint8_t prev_status = 0; - + prev_status = pdev->dev.device_status; - USBD_DCD_INT_fops->Suspend (pdev); - + USBD_DCD_INT_fops->Suspend (pdev); + dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - + /* Clear interrupt */ gintsts.d32 = 0; gintsts.b.usbsuspend = 1; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && - (pdev->dev.connection_status == 1) && + + if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) && + (pdev->dev.connection_status == 1) && (prev_status == USB_OTG_CONFIGURED)) { /* switch-off the clocks */ power.d32 = 0; power.b.stoppclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - + USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); + power.b.gatehclk = 1; USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - + /* Request to enter Sleep mode after exit from current ISR */ SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); } @@ -423,13 +425,13 @@ static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_DIEPINTn_TypeDef diepint; - + uint32_t ep_intr; uint32_t epnum = 0; uint32_t fifoemptymsk; diepint.d32 = 0; ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); - + while ( ep_intr ) { if (ep_intr&0x1) /* In ITR */ @@ -442,7 +444,7 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) CLEAR_IN_EP_INTR(epnum, xfercompl); /* TX COMPLETE */ USBD_DCD_INT_fops->DataInStage(pdev , epnum); - + if (pdev->cfg.dma_enable == 1) { if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) @@ -450,7 +452,7 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) /* prepare to rx more setup packets */ USB_OTG_EP0_OutStart(pdev); } - } + } } if ( diepint.b.timeout ) { @@ -467,19 +469,19 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) if ( diepint.b.epdisabled ) { CLEAR_IN_EP_INTR(epnum, epdisabled); - } + } if (diepint.b.emptyintr) { - + DCD_WriteEmptyTxFifo(pdev , epnum); - + CLEAR_IN_EP_INTR(epnum, emptyintr); } } epnum++; ep_intr >>= 1; } - + return 1; } @@ -495,19 +497,19 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) USB_OTG_DOEPINTn_TypeDef doepint; USB_OTG_DEPXFRSIZ_TypeDef deptsiz; uint32_t epnum = 0; - + doepint.d32 = 0; - + /* Read in the device interrupt bits */ ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); - + while ( ep_intr ) { if (ep_intr&0x1) { - + doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); - + /* Transfer complete */ if ( doepint.b.xfercompl ) { @@ -523,7 +525,7 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) /* Inform upper layer: data ready */ /* RX COMPLETE */ USBD_DCD_INT_fops->DataOutStage(pdev , epnum); - + if (pdev->cfg.dma_enable == 1) { if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) @@ -531,7 +533,7 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) /* prepare to rx more setup packets */ USB_OTG_EP0_OutStart(pdev); } - } + } } /* Endpoint disable */ if ( doepint.b.epdisabled ) @@ -542,7 +544,7 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) /* Setup Phase Done (control EPs) */ if ( doepint.b.setup ) { - + /* inform the upper layer that a setup packet is available */ /* SETUP COMPLETE */ USBD_DCD_INT_fops->SetupStage(pdev); @@ -564,15 +566,15 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_GINTSTS_TypeDef GINTSTS; - - + + USBD_DCD_INT_fops->SOF(pdev); - + /* Clear interrupt */ GINTSTS.d32 = 0; GINTSTS.b.sofintr = 1; USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); - + return 1; } @@ -587,17 +589,17 @@ static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) USB_OTG_GINTMSK_TypeDef int_mask; USB_OTG_DRXSTS_TypeDef status; USB_OTG_EP *ep; - + /* Disable the Rx Status Queue Level interrupt */ int_mask.d32 = 0; int_mask.b.rxstsqlvl = 1; USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); - + /* Get the Status from the top of the FIFO */ status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); - + ep = &pdev->dev.out_ep[status.b.epnum]; - + switch (status.b.pktsts) { case STS_GOUT_NAK: @@ -622,10 +624,10 @@ static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) default: break; } - + /* Enable the Rx Status Queue Level interrupt */ USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); - + return 1; } @@ -642,42 +644,42 @@ static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) uint32_t len = 0; uint32_t len32b; txstatus.d32 = 0; - - ep = &pdev->dev.in_ep[epnum]; - + + ep = &pdev->dev.in_ep[epnum]; + len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - + len32b = (len + 3) / 4; txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); - - - + + + while (txstatus.b.txfspcavail > len32b && ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } len32b = (len + 3) / 4; - + USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); - + ep->xfer_buff += len; ep->xfer_count += len; - + txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); } - + return 1; } @@ -696,37 +698,37 @@ static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) USB_OTG_DCTL_TypeDef dctl; USB_OTG_GINTSTS_TypeDef gintsts; uint32_t i; - + dctl.d32 = 0; daintmsk.d32 = 0; doepmsk.d32 = 0; diepmsk.d32 = 0; dcfg.d32 = 0; gintsts.d32 = 0; - + /* Clear the Remote Wake-up Signaling */ dctl.b.rmtwkupsig = 1; USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - + /* Flush the Tx FIFO */ USB_OTG_FlushTxFifo(pdev , 0 ); - + for (i = 0; i < pdev->cfg.dev_endpoints ; i++) { USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); } USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - + daintmsk.ep.in = 1; daintmsk.ep.out = 1; USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); - + doepmsk.b.setup = 1; doepmsk.b.xfercompl = 1; doepmsk.b.epdisabled = 1; USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); #endif diepmsk.b.xfercompl = 1; @@ -734,23 +736,23 @@ static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) diepmsk.b.epdisabled = 1; USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); #endif /* Reset Device Address */ dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); dcfg.b.devaddr = 0; USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); - - + + /* setup EP0 to receive SETUP packets */ USB_OTG_EP0_OutStart(pdev); - + /* Clear interrupt */ gintsts.d32 = 0; gintsts.b.usbreset = 1; USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - + /*Reset internal state machine */ USBD_DCD_INT_fops->Reset(pdev); return 1; @@ -766,28 +768,28 @@ static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) { USB_OTG_GINTSTS_TypeDef gintsts; USB_OTG_GUSBCFG_TypeDef gusbcfg; - + USB_OTG_EP0Activate(pdev); - + /* Set USB turn-around time based on device speed and PHY interface. */ gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - + /* Full or High speed */ if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) { pdev->cfg.speed = USB_OTG_SPEED_HIGH; - pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; + pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; gusbcfg.b.usbtrdtim = 9; } else { pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; + pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; gusbcfg.b.usbtrdtim = 5; } - + USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); - + /* Clear interrupt */ gintsts.d32 = 0; gintsts.b.enumdone = 1; @@ -804,16 +806,16 @@ static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) */ static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) { - USB_OTG_GINTSTS_TypeDef gintsts; - + USB_OTG_GINTSTS_TypeDef gintsts; + gintsts.d32 = 0; - USBD_DCD_INT_fops->IsoINIncomplete (pdev); - + USBD_DCD_INT_fops->IsoINIncomplete (pdev); + /* Clear interrupt */ gintsts.b.incomplisoin = 1; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - + return 1; } @@ -825,12 +827,12 @@ static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) */ static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) { - USB_OTG_GINTSTS_TypeDef gintsts; - + USB_OTG_GINTSTS_TypeDef gintsts; + gintsts.d32 = 0; - USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); - + USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); + /* Clear interrupt */ gintsts.b.incomplisoout = 1; USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); @@ -856,11 +858,11 @@ static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) /** * @} -*/ +*/ /** * @} -*/ +*/ /** * @} diff --git a/platform/mcu/STM32F4xx/linker_script.ld b/platform/mcu/STM32F4xx/linker_script.ld index b3097281..7aacbc27 100644 --- a/platform/mcu/STM32F4xx/linker_script.ld +++ b/platform/mcu/STM32F4xx/linker_script.ld @@ -12,7 +12,7 @@ /* stack top in large ram, at an address which, masked with 0x2FFE0000, gives 0x20000000 */ -_stack_top = 0x2001FFFF; +_stack_top = 0x2001FFFC; /* temporary set heap end equal to stack top */ _heap_end = _stack_top; @@ -33,13 +33,13 @@ MEMORY SECTIONS { . = 0; - + /* .text section: code goes to flash */ .text : { /* Startup code must go at address 0 */ KEEP(*(.isr_vector)) - + *(.text) *(.text.*) *(.gnu.linkonce.t.*) @@ -61,7 +61,7 @@ SECTIONS /* C++ Static constructors/destructors (eabi) */ . = ALIGN(4); KEEP(*(.init)) - + . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array))