Fixed bugs in MDx and Module17 input stream drivers causing errors in sample rate: one due to wrong configuration of TIM2 registers and one due to wrong configuration of ADC channel sample time.
This commit is contained in:
Silvano Seva
parent
3fb93f0a86
commit
4bce2c9f23
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@ -1,8 +1,8 @@
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/***************************************************************************
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* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* Copyright (C) 2021 - 2022 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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@ -25,6 +25,7 @@
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#include <hwconfig.h>
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#include <stdbool.h>
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#include <miosix.h>
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#include <timers.h>
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using namespace miosix;
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@ -120,8 +121,8 @@ streamId inputStream_start(const enum AudioSource source,
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* AP1 frequency is 42MHz but timer runs at 84MHz, tick rate is 1MHz,
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* reload register is configured based on desired sample rate.
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*/
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TIM2->PSC = 83;
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TIM2->ARR = (1000000/sampleRate) - 1;
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tim_setUpdateFreqency(TIM2, sampleRate, 84000000);
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TIM2->CNT = 0;
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TIM2->EGR = TIM_EGR_UG;
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TIM2->CR2 = TIM_CR2_MMS_1;
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@ -181,14 +182,15 @@ streamId inputStream_start(const enum AudioSource source,
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/*
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* ADC2 configuration.
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*
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* ADC clock is APB2 frequency divided by 8, giving 10.5MHz.
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* Channel sample time set to 144 cycles, total conversion time 156 cycles.
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* ADC clock is APB2 frequency divided by 4, giving 21MHz.
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* Channel sample time set to 84 cycles, total conversion time is 100
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* cycles: this leads to a maximum sampling frequency of 210kHz.
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* Convert one channel only, no overrun interrupt, 12-bit resolution,
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* no analog watchdog, discontinuous mode, no end of conversion interrupts.
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*/
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ADC->CCR |= ADC_CCR_ADCPRE;
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ADC2->SMPR2 = ADC_SMPR2_SMP2
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| ADC_SMPR2_SMP1;
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ADC->CCR |= ADC_CCR_ADCPRE_0;
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ADC2->SMPR2 = ADC_SMPR2_SMP2_2
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| ADC_SMPR2_SMP1_2;
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ADC2->SQR1 = 0; // Convert one channel
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ADC2->CR1 |= ADC_CR1_DISCEN;
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ADC2->CR2 |= ADC_CR2_EXTEN_0 // Trigger on rising edge
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@ -1,8 +1,8 @@
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/***************************************************************************
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* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* Copyright (C) 2021 - 2022 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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@ -25,6 +25,7 @@
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#include <hwconfig.h>
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#include <stdbool.h>
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#include <miosix.h>
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#include <timers.h>
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using namespace miosix;
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@ -120,8 +121,8 @@ streamId inputStream_start(const enum AudioSource source,
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* AP1 frequency is 42MHz but timer runs at 84MHz, tick rate is 1MHz,
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* reload register is configured based on desired sample rate.
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*/
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TIM2->PSC = 83;
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TIM2->ARR = (1000000/sampleRate) - 1;
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tim_setUpdateFreqency(TIM2, sampleRate, 84000000);
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TIM2->CNT = 0;
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TIM2->EGR = TIM_EGR_UG;
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TIM2->CR2 = TIM_CR2_MMS_1;
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@ -181,14 +182,15 @@ streamId inputStream_start(const enum AudioSource source,
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/*
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* ADC2 configuration.
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*
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* ADC clock is APB2 frequency divided by 8, giving 10.5MHz.
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* Channel sample time set to 144 cycles, total conversion time 156 cycles.
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* ADC clock is APB2 frequency divided by 4, giving 21MHz.
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* Channel sample time set to 84 cycles, total conversion time is 100
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* cycles: this leads to a maximum sampling frequency of 210kHz.
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* Convert one channel only, no overrun interrupt, 12-bit resolution,
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* no analog watchdog, discontinuous mode, no end of conversion interrupts.
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*/
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ADC->CCR |= ADC_CCR_ADCPRE;
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ADC2->SMPR2 = ADC_SMPR2_SMP2
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| ADC_SMPR2_SMP1;
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ADC->CCR |= ADC_CCR_ADCPRE_0;
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ADC2->SMPR2 = ADC_SMPR2_SMP2_2
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| ADC_SMPR2_SMP1_2;
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ADC2->SQR1 = 0; // Convert one channel
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ADC2->CR1 |= ADC_CR1_DISCEN;
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ADC2->CR2 |= ADC_CR2_EXTEN_0 // Trigger on rising edge
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@ -0,0 +1,72 @@
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/***************************************************************************
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* Copyright (C) 2022 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#ifndef TIMERS_H
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#define TIMERS_H
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#include <stdint.h>
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#include <stm32f4xx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Configure prescaler and auto-reload register of a timer peripheral for a
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* given update frequency.
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*
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* @param tim: timer peripheral to be configured.
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* @param updFreq: desidered update frequency, in Hz.
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* @param busFreq: frequency of the APB bus the timer is attached to, in Hz.
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* @return effective timer update frequency, in Hz.
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*/
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inline uint32_t tim_setUpdateFreqency(TIM_TypeDef *tim, uint32_t updFreq,
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uint32_t busFreq)
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{
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/*
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* Timer update frequency is given by:
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* Fupd = (Fbus / prescaler) / autoreload
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*
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* First of all we fix the prescaler to 1 and compute the autoreload: if
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* the result is greater than the maximum autoreload value, we proceed
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* iteratively.
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*/
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uint32_t psc = 1;
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uint32_t arr = busFreq/updFreq;
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while(arr >= 0xFFFF)
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{
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psc += 1;
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arr = (busFreq / psc) / updFreq;
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}
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/* Values put in registers have to be decremented by one, see RM */
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tim->PSC = psc - 1;
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tim->ARR = arr - 1;
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return (busFreq/psc)/arr;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* USART3_H */
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