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Renamed sources for SKY72310 driver

This commit is contained in:
Silvano Seva 2021-01-30 14:53:47 +01:00
parent fa07a55140
commit 5c54de0fac
4 changed files with 29 additions and 28 deletions
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4
meson.build
View File

@ -191,7 +191,7 @@ md380_src = src + stm32f405_src + ['platform/drivers/display/HX8353_MDx.c',
'platform/drivers/NVM/nvmem_MD3x0.c',
'platform/drivers/ADC/ADC1_MDx.c',
'platform/drivers/tones/toneGenerator_MDx.c',
'platform/drivers/baseband/pll_MD3x0.c',
'platform/drivers/baseband/SKY72310.c',
'platform/drivers/baseband/radio_MD3x0.c',
'platform/drivers/baseband/HR-C5000_MD3x0.c',
'platform/targets/MD-380/platform.c']
@ -208,7 +208,7 @@ md390_src = src + stm32f405_src + ['platform/drivers/display/HX8353_MDx.c',
'platform/drivers/NVM/nvmem_MD3x0.c',
'platform/drivers/ADC/ADC1_MDx.c',
'platform/drivers/tones/toneGenerator_MDx.c',
'platform/drivers/baseband/pll_MD3x0.c',
'platform/drivers/baseband/SKY72310.c',
'platform/drivers/baseband/radio_MD3x0.c',
'platform/drivers/baseband/HR-C5000_MD3x0.c',
'platform/targets/MD-390/platform.c']

16
platform/drivers/baseband/pll_MD3x0.c → platform/drivers/baseband/SKY72310.c
View File

@ -15,11 +15,11 @@
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include "pll_MD3x0.h"
#include <math.h>
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include "hwconfig.h"
#include <hwconfig.h>
#include <math.h>
#include "SKY72310.h"
#define REF_CLK 16800000.0F /* Reference clock: 16.8MHz */
#define PHD_GAIN 0x1F /* Phase detector gain: hex value, max 0x1F */
@ -58,7 +58,7 @@ void _spiSend(uint16_t value)
gpio_setPin(PLL_CS);
}
void pll_init()
void SKY73210_init()
{
gpio_setMode(PLL_CLK, OUTPUT);
gpio_setMode(PLL_DAT, OUTPUT);
@ -72,14 +72,14 @@ void pll_init()
_spiSend(0x9000); /* Modulation data register */
}
void pll_terminate()
void SKY73210_terminate()
{
gpio_setMode(PLL_CLK, INPUT);
gpio_setMode(PLL_DAT, INPUT);
gpio_setMode(PLL_CS, INPUT);
}
void pll_setFrequency(float freq, uint8_t clkDiv)
void SKY73210_setFrequency(float freq, uint8_t clkDiv)
{
/* Maximum allowable value for reference clock divider is 32 */
if (clkDiv > 32) clkDiv = 32;
@ -114,12 +114,12 @@ void pll_setFrequency(float freq, uint8_t clkDiv)
_spiSend(0x5000 | ((uint16_t)clkDiv - 1)); /* Reference clock divider */
}
bool pll_locked()
bool SKY73210_isPllLocked()
{
return (gpio_readPin(PLL_LD) == 1) ? true : false;
}
bool pll_spiInUse()
bool SKY73210_spiInUse()
{
/* If PLL chip select is low, SPI is being used by this driver. */
return (gpio_readPin(PLL_CS) == 1) ? false : true;

29
platform/drivers/baseband/pll_MD3x0.h → platform/drivers/baseband/SKY72310.h
View File

@ -15,50 +15,51 @@
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#ifndef PLL_MD3x0_H
#define PLL_MD3x0_H
#ifndef SKY73210_H
#define SKY73210_H
#include <stdint.h>
#include <stdbool.h>
/**
* Driver for PLL in MD3x0 radios (MD380 and MD380), which is SKY73210.
* Driver for SKY73210 PLL IC.
*
* WARNING: the PLL and DMR chips share the SPI MOSI line, thus particular care
* has to be put to avoid them stomping reciprocally. This driver does not make
* any check if a SPI transfer is already in progress, deferring the correct bus
* management to higher level modules. However, a function returning true if the
* bus is currently in use by this driver is provided.
* WARNING: on MD3x0 devices the PLL and DMR chips share the SPI MOSI line,
* thus particular care has to be put to avoid them stomping reciprocally.
* This driver does not make any check if a SPI transfer is already in progress,
* deferring the correct bus management to higher level modules. However,
* a function returning true if the bus is currently in use by this driver
* is provided.
*/
/**
* Initialise the PLL.
*/
void pll_init();
void SKY73210_init();
/**
* Terminate PLL driver, bringing GPIOs back to reset state.
*/
void pll_terminate();
void SKY73210_terminate();
/**
* Change VCO frequency.
* @param freq: new VCO frequency, in Hz.
* @param clkDiv: reference clock division factor.
*/
void pll_setFrequency(float freq, uint8_t clkDiv);
void SKY73210_setFrequency(float freq, uint8_t clkDiv);
/**
* Check if PLL is locked.
* @return true if PLL is locked.
*/
bool pll_locked();
bool SKY73210_isPllLocked();
/**
* Check if the SPI bus in common between PLL and DMR chips is in use by this
* driver.
* @return true if this driver is using the SPI bus.
*/
bool pll_spiInUse();
bool SKY73210_spiInUse();
#endif /* PLL_H */
#endif /* SKY73210_H */

8
platform/drivers/baseband/radio_MD3x0.c
View File

@ -29,7 +29,7 @@
#include <string.h>
#include <stdlib.h>
#include "HR-C5000_MD3x0.h"
#include "pll_MD3x0.h"
#include "SKY72310.h"
static const freq_t IF_FREQ = 49950000; /* Intermediate frequency: 49.95MHz */
@ -95,7 +95,7 @@ void radio_init()
* Enable and configure PLL
*/
gpio_setPin(PLL_PWR);
pll_init();
SKY73210_init();
/*
* Configure HR_C5000
@ -111,7 +111,7 @@ void radio_init()
void radio_terminate()
{
pll_terminate();
SKY73210_terminate();
gpio_clearPin(PLL_PWR); /* PLL off */
gpio_clearPin(DMR_SW); /* Disconnect HR_C5000 input IF signal and audio out */
@ -180,7 +180,7 @@ void radio_setVcoFrequency(const freq_t frequency, const bool isTransmitting)
freq = freq - IF_FREQ;
}
pll_setFrequency(freq, 5);
SKY73210_setFrequency(freq, 5);
}
void radio_setCSS(const tone_t rxCss, const tone_t txCss)