From 76086d567f9e42cd819ad3c83bdf244edd1fe983 Mon Sep 17 00:00:00 2001 From: Silvano Seva Date: Mon, 16 Nov 2020 11:02:31 +0100 Subject: [PATCH] Fixed regression affecting USB virtual COM port on TYT MD-380 --- .../ST/STM32F4xx/Source/system_stm32f4xx.c | 15 +++++++------ platform/mcu/STM32F4xx/drivers/usb/usb_bsp.c | 21 +++++++------------ 2 files changed, 17 insertions(+), 19 deletions(-) diff --git a/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c b/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c index 051f7a32..22bc0217 100644 --- a/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c +++ b/platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c @@ -249,7 +249,7 @@ void SystemCoreClockUpdate(void) else { /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; @@ -306,18 +306,21 @@ static void SetSysClock(void) RCC->APB1ENR |= RCC_APB1ENR_PWREN; PWR->CR |= PWR_CR_VOS; - /* HCLK = SYSCLK / 1*/ + /* HCLK = SYSCLK / 1 */ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - /* PCLK2 = HCLK / 2*/ + /* PCLK2 = HCLK / 2 */ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - /* PCLK1 = HCLK / 4*/ + /* PCLK1 = HCLK / 4 */ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 5) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + RCC->PLLCFGR = (PLL_Q << 24) /* PLL divider for USB clock */ + | RCC_PLLCFGR_PLLSRC_HSE /* HSE as PLL clock source */ + | (((PLL_P >> 1) -1) << 16) /* PLL divider for main clock */ + | (PLL_N << 6) /* PLL multiplier */ + | PLL_M; /* Input clock divider */ /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; diff --git a/platform/mcu/STM32F4xx/drivers/usb/usb_bsp.c b/platform/mcu/STM32F4xx/drivers/usb/usb_bsp.c index 33133c14..5d26b850 100644 --- a/platform/mcu/STM32F4xx/drivers/usb/usb_bsp.c +++ b/platform/mcu/STM32F4xx/drivers/usb/usb_bsp.c @@ -31,6 +31,8 @@ #include "usbd_conf.h" #include "stm32f4xx.h" #include "gpio.h" +#include +#include extern USB_OTG_CORE_HANDLE USB_OTG_dev; extern uint32_t USBD_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev); @@ -78,18 +80,9 @@ void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) * @param usec : Value of delay required in micro sec * @retval None */ -void USB_OTG_BSP_uDelay (const uint32_t usec) { - - uint32_t count = 0; - const uint32_t utime = (120 * usec / 7); - - do - { - if( ++count > utime ) - { - return ; - } - } while (1); +void USB_OTG_BSP_uDelay (const uint32_t usec) +{ + delayUs(usec); } @@ -101,11 +94,13 @@ void USB_OTG_BSP_uDelay (const uint32_t usec) { */ void USB_OTG_BSP_mDelay (const uint32_t msec) { - USB_OTG_BSP_uDelay(msec * 1000); + delayMs(msec); } void OTG_FS_IRQHandler(void) { + OSIntEnter(); USBD_OTG_ISR_Handler (&USB_OTG_dev); + OSIntExit(); }