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Fixed bad clock tree configuration for STM32F405 MCU

This commit is contained in:
Silvano Seva 2020-11-13 12:27:07 +01:00
parent a5eeca7dae
commit eb876f1b0c
2 changed files with 2 additions and 2 deletions
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2
meson.build
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@ -96,7 +96,7 @@ stm32f405_inc = ['platform/mcu/CMSIS/Include',
'rtos/uC-OS3/Ports/ARM-Cortex-M/ARMv7-M',
'rtos/uC-CPU/ARM-Cortex-M/ARMv7-M']
stm32f405_def = {'STM32F40_41xxx': ''}
stm32f405_def = {'STM32F40_41xxx': '', 'HSE_VALUE':'8000000'}
##
## Platform specializations

2
platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c
View File

@ -316,7 +316,7 @@ static void SetSysClock(void)
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
RCC->PLLCFGR = PLL_M | (PLL_N << 5) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */