Audio device driver for STM32F4xx DAC peripheral
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <kernel/scheduler/scheduler.h>
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#include <peripherals/gpio.h>
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#include <data_conversion.h>
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#include <DmaStream.hpp>
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#include <Timer.hpp>
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#include <miosix.h>
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#include <errno.h>
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#include "stm32_dac.h"
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struct ChannelState
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{
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struct streamCtx *ctx; // Current stream context
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uint32_t idleLevel; // Output idle level
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StreamHandler stream; // DMA stream handler
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};
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struct DacChannel
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{
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volatile uint32_t *dacReg; // DAC data register
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Timer tim; // TIM peripheral for DAC trigger
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};
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using Dma1_Stream5 = DmaStream< DMA1_BASE, 5, 7, 3 >; // DMA 1, Stream 5, channel 7, very high priority
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using Dma1_Stream6 = DmaStream< DMA1_BASE, 6, 7, 3 >; // DMA 1, Stream 6, channel 7, very high priority
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static constexpr DacChannel channels[] =
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{
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{&(DAC->DHR12R1), Timer(TIM6_BASE)},
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{&(DAC->DHR12R2), Timer(TIM7_BASE)},
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};
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#pragma GCC diagnostic ignored "-Wpedantic"
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struct ChannelState chState[] =
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{
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{
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.ctx = NULL,
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.idleLevel = 0,
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.stream = Dma1_Stream5::init(10, DataSize::_16BIT, 1)
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},
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{
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.ctx = NULL,
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.idleLevel = 0,
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.stream = Dma1_Stream6::init(10, DataSize::_16BIT, 1)
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}
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};
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#pragma GCC diagnostic pop
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/**
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* \internal
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* Stop an ongoing transfer, deactivating timers and DMA stream.
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*/
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static void stopTransfer(const uint8_t chNum)
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{
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channels[chNum].tim.stop();
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*channels[chNum].dacReg = chState[chNum].idleLevel;
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chState[chNum].ctx->running = 0;
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}
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/**
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* \internal
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* Actual implementation of DMA interrupt handler.
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*/
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void __attribute__((used)) DMA_Handler(uint32_t chNum)
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{
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if(chNum == 0)
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Dma1_Stream5::IRQhandleInterrupt(&chState[chNum].stream);
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else
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Dma1_Stream6::IRQhandleInterrupt(&chState[chNum].stream);
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}
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// DMA 1, Stream 5: data transfer for RTX sink
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void __attribute__((used)) DMA1_Stream5_IRQHandler()
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{
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saveContext();
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asm volatile("mov r0, #0");
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asm volatile("bl _Z11DMA_Handlerm");
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restoreContext();
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}
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// DMA 1, Stream 6: data transfer for speaker sink
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void __attribute__((used)) DMA1_Stream6_IRQHandler()
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{
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saveContext();
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asm volatile("mov r0, #1");
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asm volatile("bl _Z11DMA_Handlerm");
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restoreContext();
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}
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void stm32dac_init()
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{
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// Configure GPIOs
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gpio_setMode(GPIOA, 4, INPUT_ANALOG);
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gpio_setMode(GPIOA, 5, INPUT_ANALOG);
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// Enable peripherals
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RCC->APB1ENR |= RCC_APB1ENR_DACEN
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| RCC_APB1ENR_TIM6EN
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| RCC_APB1ENR_TIM7EN;
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__DSB();
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// DAC common configuration
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DAC->CR = DAC_CR_DMAEN2 // Enable DMA
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| DAC_CR_TSEL2_1 // TIM7 as trigger source for CH2
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| DAC_CR_TEN2 // Enable trigger input
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| DAC_CR_EN2 // Enable CH2
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| DAC_CR_DMAEN1 // Enable DMA
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| 0x00 // TIM6 as trigger source for CH1
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| DAC_CR_TEN1 // Enable trigger input
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| DAC_CR_EN1; // Enable CH1
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// Register end-of-transfer callbacks
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chState[0].stream.setEndTransferCallback(std::bind(stopTransfer, 0));
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chState[1].stream.setEndTransferCallback(std::bind(stopTransfer, 1));
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}
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void stm32dac_terminate()
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{
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// Terminate streams before shutting of the peripherals
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for(int i = 0; i < 2; i++)
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{
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if(chState[i].ctx != NULL)
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{
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if(chState[i].ctx->running != 0)
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chState[i].stream.halt();
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}
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}
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RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN |
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RCC_APB1ENR_TIM6EN |
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RCC_APB1ENR_TIM7EN);
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__DSB();
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}
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static int stm32dac_start(const uint8_t instance, const void *config,
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struct streamCtx *ctx)
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{
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if((ctx == NULL) || (ctx->running != 0))
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return -EINVAL;
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if(chState[instance].stream.running())
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return -EBUSY;
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__disable_irq();
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ctx->running = 1;
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__enable_irq();
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ctx->priv = &chState[instance];
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chState[instance].ctx = ctx;
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chState[instance].idleLevel = reinterpret_cast< uint32_t >(config);
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/*
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* Convert buffer elements from int16_t to unsigned 12 bit values as required
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* by the DAC. Processing can be done in-place because the API mandates that
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* the function caller does not modify the buffer content once this function
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* has been called.
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*/
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S16toU12(ctx->buffer, ctx->bufSize);
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bool circ = false;
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if(ctx->bufMode == BUF_CIRC_DOUBLE)
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circ = true;
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chState[instance].stream.start(channels[instance].dacReg, ctx->buffer,
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ctx->bufSize, circ);
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// Configure DAC trigger
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channels[instance].tim.setUpdateFrequency(ctx->sampleRate);
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channels[instance].tim.start();
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return 0;
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}
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static int stm32dac_idleBuf(struct streamCtx *ctx, stream_sample_t **buf)
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{
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ChannelState *state = reinterpret_cast< ChannelState * >(ctx->priv);
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*buf = reinterpret_cast< stream_sample_t *>(state->stream.idleBuf());
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return ctx->bufSize/2;
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}
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static int stm32dac_sync(struct streamCtx *ctx, uint8_t dirty)
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{
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ChannelState *state = reinterpret_cast< ChannelState * >(ctx->priv);
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if((ctx->bufMode == BUF_CIRC_DOUBLE) && (dirty != 0))
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{
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void *ptr = state->stream.idleBuf();
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S16toU12(reinterpret_cast< int16_t *>(ptr), ctx->bufSize/2);
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}
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bool ok = state->stream.sync();
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if(ok) return 0;
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return -1;
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}
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static void stm32dac_stop(struct streamCtx *ctx)
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{
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if(ctx->running == 0)
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return;
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reinterpret_cast< ChannelState * >(ctx->priv)->stream.stop();
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}
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static void stm32dac_halt(struct streamCtx *ctx)
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{
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if(ctx->running == 0)
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return;
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reinterpret_cast< ChannelState * >(ctx->priv)->stream.halt();
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}
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#pragma GCC diagnostic ignored "-Wpedantic"
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const struct audioDriver stm32_dac_audio_driver =
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{
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.start = stm32dac_start,
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.data = stm32dac_idleBuf,
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.sync = stm32dac_sync,
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.stop = stm32dac_stop,
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.terminate = stm32dac_halt
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};
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#pragma GCC diagnostic pop
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@ -0,0 +1,74 @@
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#ifndef STM32_DAC_H
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#define STM32_DAC_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stm32f4xx.h>
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#include <interfaces/audio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Driver for STM32F4xx DAC peripheral used as audio output stream device.
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* Input data format is signed 16-bit, internally converted to unsigned 12-bit
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* values for compatibility with the hardware.
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*
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* This driver has two instances:
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*
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* - instance 0: DAC_CH1, DMA1_Stream5, TIM6,
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* - instance 1: DAC_CH2, DMA1_Stream6, TIM7
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*
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* The possible configuration for each channel is the idle level for the DAC
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* output, ranging from 0 to 4096. Idle level is passed by value directly in the
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* config field.
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*/
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enum Stm32DacInstance
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{
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STM32_DAC_CH1 = 0,
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STM32_DAC_CH2,
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};
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extern const struct audioDriver stm32_dac_audio_driver;
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/**
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* Initialize the driver and the peripherals.
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*/
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void stm32dac_init();
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/**
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* Shutdown the driver and the peripherals.
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*/
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void stm32dac_terminate();
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32_DAC_H */
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