From f0862abac19b08cc0dcef9fd194eac78e5b091f1 Mon Sep 17 00:00:00 2001 From: Silvano Seva Date: Sat, 19 Dec 2020 10:12:05 +0100 Subject: [PATCH] On MD3x0 baseband, fixed PLL going nuts for some frequencies (e.g. 430.0MHz) and causing the radio transmitting on a shifted band. --- platform/drivers/baseband/pll_MD3x0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/platform/drivers/baseband/pll_MD3x0.c b/platform/drivers/baseband/pll_MD3x0.c index 69b7f088..8833c18a 100644 --- a/platform/drivers/baseband/pll_MD3x0.c +++ b/platform/drivers/baseband/pll_MD3x0.c @@ -88,6 +88,22 @@ void pll_setFrequency(float freq, uint8_t clkDiv) float Ndiv = floor(K) - 32.0; float Ndnd = round(262144*(K - Ndiv - 32.0)); + /* + * With PLL in fractional mode, dividend range is [-131017 +131071]. If our + * computation gives a wrong result, we decrement the reference clock divider + * and redo the computations. + * + * TODO: better investigate on how to put PLL in unsigned dividend mode. + */ + if(((uint32_t) Ndnd) >= 131070) + { + clkDiv -= 1; + K = freq/(REF_CLK/((float) clkDiv)); + Ndiv = floor(K) - 32.0; + Ndnd = round(262144*(K - Ndiv - 32.0)); + + } + uint32_t dnd = ((uint32_t) Ndnd); uint16_t dndMsb = dnd >> 8; uint16_t dndLsb = dnd & 0x00FF;