diff --git a/platform/drivers/baseband/HR_C5000_MDx.cpp b/platform/drivers/baseband/HR_C5000_MDx.cpp
index f828046a..5d0a8584 100644
--- a/platform/drivers/baseband/HR_C5000_MDx.cpp
+++ b/platform/drivers/baseband/HR_C5000_MDx.cpp
@@ -47,16 +47,16 @@ template< class M >
 void HR_Cx000< M >::init()
 {
     gpio_setMode(DMR_SLEEP, OUTPUT);
-    gpio_clearPin(DMR_SLEEP);             // Exit from sleep pulling down DMR_SLEEP
+    gpio_clearPin(DMR_SLEEP);           // Exit from sleep pulling down DMR_SLEEP
 
-    writeReg(M::CONFIG, 0x0A, 0x80);      // Internal clock connected to crystal
-    writeReg(M::CONFIG, 0x0B, 0x28);      // PLL M register (multiplier)
-    writeReg(M::CONFIG, 0x0C, 0x33);      // PLL input and output dividers
+    writeReg(M::CONFIG, 0x0A, 0x80);    // Internal clock connected to crystal
+    writeReg(M::CONFIG, 0x0B, 0x28);    // PLL M register (multiplier)
+    writeReg(M::CONFIG, 0x0C, 0x33);    // PLL input and output dividers
 
     delayMs(1);
-    writeReg(M::CONFIG, 0x0A, 0x00);      // Internal clock connected to PLL
-    writeReg(M::CONFIG, 0xBA, 0x22);      // Built-in codec clock freq. (HR_C6000)
-    writeReg(M::CONFIG, 0xBB, 0x11);      // Output clock operating freq. (HR_C6000)
+    writeReg(M::CONFIG, 0x0A, 0x00);    // Internal clock connected to PLL
+    writeReg(M::CONFIG, 0xBA, 0x22);    // Built-in codec clock freq. (HR_C6000)
+    writeReg(M::CONFIG, 0xBB, 0x11);    // Output clock operating freq. (HR_C6000)
 }
 
 template< class M >
@@ -158,9 +158,6 @@ void HR_Cx000< M >::fmMode()
     sendSequence(initSeq2, sizeof(initSeq2));
     writeReg(M::CONFIG, 0x0D, 0x8C);    // Codec control
     writeReg(M::CONFIG, 0x0E, 0x40);    // Mute HPout
-//     writeReg(M::CONFIG, 0x0F, 0xC8);    // ADLinVol, mic volume
-//     writeReg(M::CONFIG, 0x25, 0x0E);
-//     writeReg(M::CONFIG, 0x26, 0xFE);
     writeReg(M::CONFIG, 0x83, 0xFF);    // Clear all interrupt flags
     writeReg(M::CONFIG, 0x87, 0x00);    // Disable "stop" interrupts
     writeReg(M::CONFIG, 0x81, 0x00);    // Mask other interrupts
@@ -168,8 +165,8 @@ void HR_Cx000< M >::fmMode()
     writeReg(M::CONFIG, 0x00, 0x28);    // Reset register
 }
 
-template< class M>
-void HR_Cx000<M>::startAnalogTx(const TxAudioSource source, const FmConfig cfg)
+template< class M >
+void HR_Cx000< M >::startAnalogTx(const TxAudioSource source, const FmConfig cfg)
 {
     uint8_t audioCfg = 0x40;                                // Mute HPout
     if(source == TxAudioSource::MIC)     audioCfg |= 0x04;  // Mic1En
@@ -177,14 +174,9 @@ void HR_Cx000<M>::startAnalogTx(const TxAudioSource source, const FmConfig cfg)
 
     writeReg(M::CONFIG, 0x0D, 0x8C);    // Codec control
     writeReg(M::CONFIG, 0x0E, audioCfg);
-//     writeReg(M::CONFIG, 0x0F, 0xC8);    // ADLinVol, mic volume
-//     writeReg(M::CONFIG, 0x25, 0x0E);
-//     writeReg(M::CONFIG, 0x26, 0xFE);
     writeReg(M::CONFIG, 0x34, static_cast< uint8_t >(cfg));
     writeReg(M::CONFIG, 0x3E, 0x08);    // "FM Modulation frequency deviation coefficient at the receiving end" (HR_C6000)
     writeReg(M::CONFIG, 0x37, 0xC2);    // Unknown register
-//     writeReg(M::AUX, 0x50, 0x00);
-//     writeReg(M::AUX, 0x51, 0x00);
     writeReg(M::CONFIG, 0x60, 0x80);    // Enable analog voice transmission
 }
 
@@ -197,8 +189,8 @@ void HR_Cx000< M >::stopAnalogTx()
 /*
  * SPI interface driver
  */
-template<class M>
-void HR_Cx000<M>::uSpi_init()
+template< class M >
+void HR_Cx000< M >::uSpi_init()
 {
     gpio_setMode(DMR_CS,    OUTPUT);
     gpio_setMode(DMR_CLK,   OUTPUT);
diff --git a/platform/drivers/baseband/HR_C6000_GDx.cpp b/platform/drivers/baseband/HR_C6000_GDx.cpp
index 400da6b6..011e9844 100644
--- a/platform/drivers/baseband/HR_C6000_GDx.cpp
+++ b/platform/drivers/baseband/HR_C6000_GDx.cpp
@@ -61,14 +61,14 @@ void HR_Cx000< M >::init()
     gpio_setPin(DMR_SLEEP);
 
     delayMs(10);
-    gpio_clearPin(DMR_SLEEP);           //Exit from sleep pulling down DMR_SLEEP
+    gpio_clearPin(DMR_SLEEP);           // Exit from sleep pulling down DMR_SLEEP
     delayMs(10);
 
-    writeReg(M::CONFIG, 0x0A, 0x81);    //Clock connected to crystal
-    writeReg(M::CONFIG, 0x0B, 0x40);    //Set PLL M Register
-    writeReg(M::CONFIG, 0x0C, 0x32);    //Set PLL Dividers
+    writeReg(M::CONFIG, 0x0A, 0x81);    // Clock connected to crystal
+    writeReg(M::CONFIG, 0x0B, 0x40);    // Set PLL M Register
+    writeReg(M::CONFIG, 0x0C, 0x32);    // Set PLL Dividers
     writeReg(M::CONFIG, 0xB9, 0x05);
-    writeReg(M::CONFIG, 0x0A, 0x01);    //Clock connected to PLL, set Clock Source Enable CLKOUT Pin
+    writeReg(M::CONFIG, 0x0A, 0x01);    // Clock connected to PLL, set Clock Source Enable CLKOUT Pin
 
     sendSequence(initSeq1, sizeof(initSeq1));
     sendSequence(initSeq2, sizeof(initSeq2));
@@ -77,63 +77,63 @@ void HR_Cx000< M >::init()
     sendSequence(initSeq5, sizeof(initSeq5));
     sendSequence(initSeq6, sizeof(initSeq6));
 
-    writeReg(M::CONFIG, 0x00, 0x00);   //Clear all Reset Bits which forces a reset of all internal systems
-    writeReg(M::CONFIG, 0x10, 0x6E);   //Set DMR,Tier2,Timeslot Mode, Layer 2, Repeater, Aligned, Slot1
-    writeReg(M::CONFIG, 0x11, 0x80);   //Set LocalChanMode to Default Value
-    writeReg(M::CONFIG, 0x13, 0x00);   //Zero Cend_Band Timing advance
-    writeReg(M::CONFIG, 0x1F, 0x10);   //Set LocalEMB  DMR Colour code in upper 4 bits - defaulted to 1, and is updated elsewhere in the code
-    writeReg(M::CONFIG, 0x20, 0x00);   //Set LocalAccessPolicy to Impolite
-    writeReg(M::CONFIG, 0x21, 0xA0);   //Set LocalAccessPolicy1 to Polite to Color Code  (unsure why there are two registers for this)
-    writeReg(M::CONFIG, 0x22, 0x26);   //Start Vocoder Decode, I2S mode
-    writeReg(M::CONFIG, 0x22, 0x86);   //Start Vocoder Encode, I2S mode
-    writeReg(M::CONFIG, 0x25, 0x0E);   //Undocumented Register
-    writeReg(M::CONFIG, 0x26, 0x7D);   //Undocumented Register
-    writeReg(M::CONFIG, 0x27, 0x40);   //Undocumented Register
-    writeReg(M::CONFIG, 0x28, 0x7D);   //Undocumented Register
-    writeReg(M::CONFIG, 0x29, 0x40);   //Undocumented Register
-    writeReg(M::CONFIG, 0x2A, 0x0B);   //Set spi_clk_cnt to default value
-    writeReg(M::CONFIG, 0x2B, 0x0B);   //According to Datasheet this is a Read only register For FM Squelch
-    writeReg(M::CONFIG, 0x2C, 0x17);   //According to Datasheet this is a Read only register For FM Squelch
-    writeReg(M::CONFIG, 0x2D, 0x05);   //Set FM Compression and Decompression points (?)
-    writeReg(M::CONFIG, 0x2E, 0x04);   //Set tx_pre_on (DMR Transmission advance) to 400us
-    writeReg(M::CONFIG, 0x2F, 0x0B);   //Set I2S Clock Frequency
-    writeReg(M::CONFIG, 0x32, 0x02);   //Set LRCK_CNT_H CODEC Operating Frequency to default value
-    writeReg(M::CONFIG, 0x33, 0xFF);   //Set LRCK_CNT_L CODEC Operating Frequency to default value
-    writeReg(M::CONFIG, 0x34, 0xF0);   //Set FM Filters on and bandwidth to 12.5Khz
-    writeReg(M::CONFIG, 0x35, 0x28);   //Set FM Modulation Coefficient
-    writeReg(M::CONFIG, 0x3E, 0x28);   //Set FM Modulation Offset
-    writeReg(M::CONFIG, 0x3F, 0x10);   //Set FM Modulation Limiter
-    writeReg(M::CONFIG, 0x36, 0x00);   //Enable all clocks
-    writeReg(M::CONFIG, 0x37, 0x00);   //Set mcu_control_shift to default. (codec under HRC-6000 control)
-    writeReg(M::CONFIG, 0x4B, 0x1B);   //Set Data packet types to defaults
-    writeReg(M::CONFIG, 0x4C, 0x00);   //Set Data packet types to defaults
-    writeReg(M::CONFIG, 0x56, 0x00);   //Undocumented Register
-    writeReg(M::CONFIG, 0x5F, 0xC0);   //Enable Sync detection for MS or BS orignated signals
-    writeReg(M::CONFIG, 0x81, 0xFF);   //Enable all Interrupts
-    writeReg(M::CONFIG, 0xD1, 0xC4);   //According to Datasheet this register is for FM DTMF (?)
+    writeReg(M::CONFIG, 0x00, 0x00);   // Reset of all internal systems
+    writeReg(M::CONFIG, 0x10, 0x6E);   // Set DMR, Tier2, Timeslot Mode, Layer 2, Repeater, Aligned, Slot1
+    writeReg(M::CONFIG, 0x11, 0x80);   // Set LocalChanMode to Default Value
+    writeReg(M::CONFIG, 0x13, 0x00);   // Zero Cend_Band Timing advance
+    writeReg(M::CONFIG, 0x1F, 0x10);   // Set LocalEMB  DMR Colour code in upper 4 bits - defaulted to 1, and is updated elsewhere in the code
+    writeReg(M::CONFIG, 0x20, 0x00);   // Set LocalAccessPolicy to Impolite
+    writeReg(M::CONFIG, 0x21, 0xA0);   // Set LocalAccessPolicy1 to Polite to Color Code  (unsure why there are two registers for this)
+    writeReg(M::CONFIG, 0x22, 0x26);   // Start Vocoder Decode, I2S mode
+    writeReg(M::CONFIG, 0x22, 0x86);   // Start Vocoder Encode, I2S mode
+    writeReg(M::CONFIG, 0x25, 0x0E);   // Undocumented Register
+    writeReg(M::CONFIG, 0x26, 0x7D);   // Undocumented Register
+    writeReg(M::CONFIG, 0x27, 0x40);   // Undocumented Register
+    writeReg(M::CONFIG, 0x28, 0x7D);   // Undocumented Register
+    writeReg(M::CONFIG, 0x29, 0x40);   // Undocumented Register
+    writeReg(M::CONFIG, 0x2A, 0x0B);   // Set spi_clk_cnt to default value
+    writeReg(M::CONFIG, 0x2B, 0x0B);   // According to Datasheet this is a Read only register For FM Squelch
+    writeReg(M::CONFIG, 0x2C, 0x17);   // According to Datasheet this is a Read only register For FM Squelch
+    writeReg(M::CONFIG, 0x2D, 0x05);   // Set FM Compression and Decompression points (?)
+    writeReg(M::CONFIG, 0x2E, 0x04);   // Set tx_pre_on (DMR Transmission advance) to 400us
+    writeReg(M::CONFIG, 0x2F, 0x0B);   // Set I2S Clock Frequency
+    writeReg(M::CONFIG, 0x32, 0x02);   // Set LRCK_CNT_H CODEC Operating Frequency to default value
+    writeReg(M::CONFIG, 0x33, 0xFF);   // Set LRCK_CNT_L CODEC Operating Frequency to default value
+    writeReg(M::CONFIG, 0x34, 0xF0);   // Set FM Filters on and bandwidth to 12.5Khz
+    writeReg(M::CONFIG, 0x35, 0x28);   // Set FM Modulation Coefficient
+    writeReg(M::CONFIG, 0x3E, 0x28);   // Set FM Modulation Offset
+    writeReg(M::CONFIG, 0x3F, 0x10);   // Set FM Modulation Limiter
+    writeReg(M::CONFIG, 0x36, 0x00);   // Enable all clocks
+    writeReg(M::CONFIG, 0x37, 0x00);   // Set mcu_control_shift to default. (codec under HRC-6000 control)
+    writeReg(M::CONFIG, 0x4B, 0x1B);   // Set Data packet types to defaults
+    writeReg(M::CONFIG, 0x4C, 0x00);   // Set Data packet types to defaults
+    writeReg(M::CONFIG, 0x56, 0x00);   // Undocumented Register
+    writeReg(M::CONFIG, 0x5F, 0xC0);   // Enable Sync detection for MS or BS orignated signals
+    writeReg(M::CONFIG, 0x81, 0xFF);   // Enable all Interrupts
+    writeReg(M::CONFIG, 0xD1, 0xC4);   // According to Datasheet this register is for FM DTMF
 
-    writeReg(M::CONFIG, 0x01, 0x70);   //set 2 point Mod, swap receive I and Q, receive mode IF (?)    (Presumably changed elsewhere)
-    writeReg(M::CONFIG, 0x03, 0x00);   //zero Receive I Offset
-    writeReg(M::CONFIG, 0x05, 0x00);   //Zero Receive Q Offset
-    writeReg(M::CONFIG, 0x12, 0x15);   //Set rf_pre_on Receive to transmit switching advance
-    writeReg(M::CONFIG, 0xA1, 0x80);   //According to Datasheet this register is for FM Modulation Setting (?)
-    writeReg(M::CONFIG, 0xC0, 0x0A);   //Set RF Signal Advance to 1ms (10x100us)
-    writeReg(M::CONFIG, 0x06, 0x21);   //Use SPI vocoder under MCU control
-    writeReg(M::CONFIG, 0x07, 0x0B);   //Set IF Frequency H to default 450KHz
-    writeReg(M::CONFIG, 0x08, 0xB8);   //Set IF Frequency M to default 450KHz
-    writeReg(M::CONFIG, 0x09, 0x00);   //Set IF Frequency L to default 450KHz
-    writeReg(M::CONFIG, 0x0D, 0x10);   //Set Voice Superframe timeout value
-    writeReg(M::CONFIG, 0x0E, 0x8E);   //Register Documented as Reserved
-    writeReg(M::CONFIG, 0x0F, 0xB8);   //FSK Error Count
-    writeReg(M::CONFIG, 0xC2, 0x00);   //Disable Mic Gain AGC
-    writeReg(M::CONFIG, 0xE0, 0x8B);   //CODEC under MCU Control, LineOut2 Enabled, Mic_p Enabled, I2S Slave Mode
-    writeReg(M::CONFIG, 0xE1, 0x0F);   //Undocumented Register (Probably associated with CODEC)
-    writeReg(M::CONFIG, 0xE2, 0x06);   //CODEC  Anti Pop Enabled, DAC Output Enabled
-    writeReg(M::CONFIG, 0xE3, 0x52);   //CODEC Default Settings
-    writeReg(M::CONFIG, 0xE4, 0x4A);   //CODEC   LineOut Gain 2dB, Mic Stage 1 Gain 0dB, Mic Stage 2 Gain 30dB
-    writeReg(M::CONFIG, 0xE5, 0x1A);   //CODEC Default Setting
-    writeReg(M::CONFIG, 0x40, 0xC3);   //Enable DMR Tx, DMR Rx, Passive Timing, Normal mode
-    writeReg(M::CONFIG, 0x41, 0x40);   //Receive during next timeslot
+    writeReg(M::CONFIG, 0x01, 0x70);   // set 2 point Mod, swap receive I and Q, receive mode IF
+    writeReg(M::CONFIG, 0x03, 0x00);   // zero Receive I Offset
+    writeReg(M::CONFIG, 0x05, 0x00);   // Zero Receive Q Offset
+    writeReg(M::CONFIG, 0x12, 0x15);   // Set rf_pre_on Receive to transmit switching advance
+    writeReg(M::CONFIG, 0xA1, 0x80);   // According to Datasheet this register is for FM Modulation Setting (?)
+    writeReg(M::CONFIG, 0xC0, 0x0A);   // Set RF Signal Advance to 1ms (10x100us)
+    writeReg(M::CONFIG, 0x06, 0x21);   // Use SPI vocoder under MCU control
+    writeReg(M::CONFIG, 0x07, 0x0B);   // Set IF Frequency H to default 450KHz
+    writeReg(M::CONFIG, 0x08, 0xB8);   // Set IF Frequency M to default 450KHz
+    writeReg(M::CONFIG, 0x09, 0x00);   // Set IF Frequency L to default 450KHz
+    writeReg(M::CONFIG, 0x0D, 0x10);   // Set Voice Superframe timeout value
+    writeReg(M::CONFIG, 0x0E, 0x8E);   // Register Documented as Reserved
+    writeReg(M::CONFIG, 0x0F, 0xB8);   // FSK Error Count
+    writeReg(M::CONFIG, 0xC2, 0x00);   // Disable Mic Gain AGC
+    writeReg(M::CONFIG, 0xE0, 0x8B);   // CODEC under MCU Control, LineOut2 Enabled, Mic_p Enabled, I2S Slave Mode
+    writeReg(M::CONFIG, 0xE1, 0x0F);   // Undocumented Register (Probably associated with CODEC)
+    writeReg(M::CONFIG, 0xE2, 0x06);   // CODEC  Anti Pop Enabled, DAC Output Enabled
+    writeReg(M::CONFIG, 0xE3, 0x52);   // CODEC Default Settings
+    writeReg(M::CONFIG, 0xE4, 0x4A);   // CODEC   LineOut Gain 2dB, Mic Stage 1 Gain 0dB, Mic Stage 2 Gain 30dB
+    writeReg(M::CONFIG, 0xE5, 0x1A);   // CODEC Default Setting
+    writeReg(M::CONFIG, 0x40, 0xC3);   // Enable DMR Tx, DMR Rx, Passive Timing, Normal mode
+    writeReg(M::CONFIG, 0x41, 0x40);   // Receive during next timeslot
 }
 
 template< class M >
@@ -149,8 +149,8 @@ void HR_Cx000< M >::setModOffset(const uint16_t offset)
     uint8_t offUpper = (offset >> 8) & 0x03;
     uint8_t offLower = offset & 0xFF;
 
-    writeReg(M::CONFIG, 0x48, offUpper);
-    writeReg(M::CONFIG, 0x47, offLower);
+    writeReg(M::CONFIG, 0x48, offUpper);    // Two-point bias, upper value
+    writeReg(M::CONFIG, 0x47, offLower);    // Two-point bias, lower value
 }
 
 // Unused functionalities on GDx
diff --git a/platform/drivers/baseband/HR_C6000_UV3x0.cpp b/platform/drivers/baseband/HR_C6000_UV3x0.cpp
index b64b47ea..4fc23c4c 100644
--- a/platform/drivers/baseband/HR_C6000_UV3x0.cpp
+++ b/platform/drivers/baseband/HR_C6000_UV3x0.cpp
@@ -58,33 +58,33 @@ void HR_Cx000< M >::init()
     gpio_setPin(DMR_SLEEP);
 
     delayMs(10);
-    gpio_clearPin(DMR_SLEEP);         // Exit from sleep pulling down DMR_SLEEP
+    gpio_clearPin(DMR_SLEEP);           // Exit from sleep pulling down DMR_SLEEP
     delayMs(10);
 
-    writeReg(M::CONFIG, 0x0A, 0x80);    //Clock connected to crystal
-    writeReg(M::CONFIG, 0x0B, 0x28);    //Set PLL M Register
-    writeReg(M::CONFIG, 0x0C, 0x33);    //Set PLL Dividers
+    writeReg(M::CONFIG, 0x0A, 0x80);    // Clock connected to crystal
+    writeReg(M::CONFIG, 0x0B, 0x28);    // Set PLL M Register
+    writeReg(M::CONFIG, 0x0C, 0x33);    // Set PLL Dividers
     delayMs(250);
 
-    writeReg(M::CONFIG, 0x0A, 0x00);
-    writeReg(M::CONFIG, 0xB9, 0x05);
-    writeReg(M::CONFIG, 0xBA, 0x04);
-    writeReg(M::CONFIG, 0xBB, 0x02);
-    writeReg(M::CONFIG, 0xA1, 0x80);
-    writeReg(M::CONFIG, 0x10, 0xF3);
-    writeReg(M::CONFIG, 0x40, 0x43);
-    writeReg(M::CONFIG, 0x07, 0x0B);
-    writeReg(M::CONFIG, 0x08, 0xB8);
-    writeReg(M::CONFIG, 0x09, 0x00);
+    writeReg(M::CONFIG, 0x0A, 0x00);    // Clock connected to PLL
+    writeReg(M::CONFIG, 0xB9, 0x05);    // System clock frequency
+    writeReg(M::CONFIG, 0xBA, 0x04);    // Codec clock frequency
+    writeReg(M::CONFIG, 0xBB, 0x02);    // Output clock frequency
+    writeReg(M::CONFIG, 0xA1, 0x80);    // FM_mod, all modes cleared
+    writeReg(M::CONFIG, 0x10, 0xF3);    // FM mode, Tier II, TimeSlot, 3rd layer mode, aligned (?)
+    writeReg(M::CONFIG, 0x40, 0x43);    // Enable RX synchronisation, normal mode (no test)
+    writeReg(M::CONFIG, 0x07, 0x0B);    // IF frequency - high 8 bit
+    writeReg(M::CONFIG, 0x08, 0xB8);    // IF frequency - mid 8 bit
+    writeReg(M::CONFIG, 0x09, 0x00);    // IF frequency - low 8 bit
     sendSequence(initSeq1, sizeof(initSeq1));
-    writeReg(M::CONFIG, 0x01, 0xF8);
+    writeReg(M::CONFIG, 0x01, 0xF8);    // Swap TX IQ, swap RX IQ, two point mode for TX, baseband IQ mode for RX
     sendSequence(initSeq2, sizeof(initSeq2));
-    writeReg(M::CONFIG, 0x00, 0x2A);
+    writeReg(M::CONFIG, 0x00, 0x2A);    // Reset codec, reset vocoder, reset I2S
 
-    writeReg(M::CONFIG, 0x06, 0x20);
-    writeReg(M::CONFIG, 0x14, 0x59);
-    writeReg(M::CONFIG, 0x15, 0xF5);
-    writeReg(M::CONFIG, 0x16, 0x21);
+    writeReg(M::CONFIG, 0x06, 0x20);    // Vocoder output connected to universal interface (?)
+    writeReg(M::CONFIG, 0x14, 0x59);    // local address - low 8 bit
+    writeReg(M::CONFIG, 0x15, 0xF5);    // local address - mid 8 bit
+    writeReg(M::CONFIG, 0x16, 0x21);    // local address - high 8 bit
     sendSequence(initSeq3, sizeof(initSeq3));
     sendSequence(initSeq4, sizeof(initSeq4));
     sendSequence(initSeq5, sizeof(initSeq5));
@@ -95,22 +95,22 @@ void HR_Cx000< M >::init()
     writeReg(M::AUX,    0x45, 0x1E);
     writeReg(M::AUX,    0x37, 0x50);
     writeReg(M::AUX,    0x35, 0xFF);
-    writeReg(M::CONFIG, 0x39, 0x02);
-    writeReg(M::CONFIG, 0x3D, 0x0A);
-    writeReg(M::CONFIG, 0x83, 0xFF);
-    writeReg(M::CONFIG, 0x87, 0x00);
-    writeReg(M::CONFIG, 0x65, 0x0A);
-    writeReg(M::CONFIG, 0x1D, 0xFF);
-    writeReg(M::CONFIG, 0x1E, 0xF1);
-    writeReg(M::CONFIG, 0xE2, 0x06);
-    writeReg(M::CONFIG, 0xE4, 0x27);
-    writeReg(M::CONFIG, 0xE3, 0x52);
-    writeReg(M::CONFIG, 0xE5, 0x1A);
-    writeReg(M::CONFIG, 0xE1, 0x0F);
-    writeReg(M::CONFIG, 0xD1, 0xC4);
-    writeReg(M::CONFIG, 0x25, 0x0E);
-    writeReg(M::CONFIG, 0x26, 0xFD);
-    writeReg(M::CONFIG, 0x64, 0x00);
+    writeReg(M::CONFIG, 0x39, 0x02);    // Undocumented register
+    writeReg(M::CONFIG, 0x3D, 0x0A);    // Undocumented register
+    writeReg(M::CONFIG, 0x83, 0xFF);    // Clear all interrupt flags
+    writeReg(M::CONFIG, 0x87, 0x00);    // Disable all interrupt sources
+    writeReg(M::CONFIG, 0x65, 0x0A);    // Undocumented register
+    writeReg(M::CONFIG, 0x1D, 0xFF);    // Local unaddress, mask unaddress (?)
+    writeReg(M::CONFIG, 0x1E, 0xF1);    // Broadcast RX address, broadcast address mask
+    writeReg(M::CONFIG, 0xE2, 0x06);    // Mic preamp disabled, anti-pop enabled
+    writeReg(M::CONFIG, 0xE4, 0x27);    // Lineout gain, first and second stage mic gain
+    writeReg(M::CONFIG, 0xE3, 0x52);    // Internal ADC and DAC passthrough enable
+    writeReg(M::CONFIG, 0xE5, 0x1A);    // Undocumented register
+    writeReg(M::CONFIG, 0xE1, 0x0F);    // Undocumented register
+    writeReg(M::CONFIG, 0xD1, 0xC4);    // DTMF code width (?)
+    writeReg(M::CONFIG, 0x25, 0x0E);    // Undocumented register
+    writeReg(M::CONFIG, 0x26, 0xFD);    // Undocumented register
+    writeReg(M::CONFIG, 0x64, 0x00);    // Undocumented register
 }
 
 template< class M >
@@ -142,54 +142,54 @@ void HR_Cx000< M >::setModOffset(const uint16_t offset)
 template< class M >
 void HR_Cx000< M >::dmrMode()
 {
-    writeReg(M::CONFIG, 0x10, 0x4F);
-    writeReg(M::CONFIG, 0x81, 0x19);
-    writeReg(M::CONFIG, 0x01, 0xF0);
-    writeReg(M::CONFIG, 0xE4, 0x27);
-    writeReg(M::CONFIG, 0xE5, 0x1A);
-    writeReg(M::CONFIG, 0x25, 0x0E);
-    writeReg(M::CONFIG, 0x26, 0xFD);
+    writeReg(M::CONFIG, 0x10, 0x4F);    // DMR mode, Tier I, TimeSlot, 2nd layer mode, relay, aligned (?)
+    writeReg(M::CONFIG, 0x81, 0x19);    // Interrupt mask
+    writeReg(M::CONFIG, 0x01, 0xF0);    // Swap TX IQ, swap RX IQ, two point mode for TX, IF mode for RX
+    writeReg(M::CONFIG, 0xE4, 0x27);    // Lineout gain, first and second stage mic gain
+    writeReg(M::CONFIG, 0xE5, 0x1A);    // Undocumented register
+    writeReg(M::CONFIG, 0x25, 0x0E);    // Undocumented register
+    writeReg(M::CONFIG, 0x26, 0xFD);    // Undocumented register
     writeReg(M::AUX,    0x54, 0x78);
-    writeReg(M::CONFIG, 0x1F, 0x10);
+    writeReg(M::CONFIG, 0x1F, 0x10);    // Color code, encryption disabled
     writeReg(M::AUX,    0x24, 0x00);
     writeReg(M::AUX,    0x25, 0x00);
     writeReg(M::AUX,    0x26, 0x00);
     writeReg(M::AUX,    0x27, 0x00);
-    writeReg(M::CONFIG, 0x41, 0x40);
-    writeReg(M::CONFIG, 0x56, 0x00);
-    writeReg(M::CONFIG, 0x41, 0x40);
-    writeReg(M::CONFIG, 0x5C, 0x09);
-    writeReg(M::CONFIG, 0x5F, 0xC0);
+    writeReg(M::CONFIG, 0x41, 0x40);    // Start RX for upcoming time slot interrupt
+    writeReg(M::CONFIG, 0x56, 0x00);    // Undocumented register
+    writeReg(M::CONFIG, 0x41, 0x40);    // Start RX for upcoming time slot interrupt
+    writeReg(M::CONFIG, 0x5C, 0x09);    // Undocumented register
+    writeReg(M::CONFIG, 0x5F, 0xC0);    // Detect BS and MS frame sequences in 2 layer mode
     sendSequence(initSeq7, sizeof(initSeq7));
-    writeReg(M::CONFIG, 0x11, 0x80);
+    writeReg(M::CONFIG, 0x11, 0x80);    // Local channel mode
 }
 
 template< class M >
 void HR_Cx000< M >::fmMode()
 {
-    writeReg(M::CONFIG, 0x10, 0xF3);
-    writeReg(M::CONFIG, 0x01, 0xB0);
-    writeReg(M::CONFIG, 0x81, 0x04);
-    writeReg(M::CONFIG, 0xE5, 0x1A);
-    writeReg(M::CONFIG, 0x36, 0x02);
-    writeReg(M::CONFIG, 0xE4, 0x27);
-    writeReg(M::CONFIG, 0xE2, 0x06);
-    writeReg(M::CONFIG, 0x34, 0x98);
-    writeReg(M::CONFIG, 0x60, 0x00);
-    writeReg(M::CONFIG, 0x1F, 0x00);
+    writeReg(M::CONFIG, 0x10, 0xF3);    // FM mode, Tier II, TimeSlot, 3rd layer mode, aligned (?)
+    writeReg(M::CONFIG, 0x01, 0xB0);    // Swap TX IQ, two point mode for TX, IF mode for RX
+    writeReg(M::CONFIG, 0x81, 0x04);    // Interrupt mask
+    writeReg(M::CONFIG, 0xE5, 0x1A);    // Undocumented register
+    writeReg(M::CONFIG, 0x36, 0x02);    // Enable voice channel in FM mode
+    writeReg(M::CONFIG, 0xE4, 0x27);    // Lineout gain, first and second stage mic gain
+    writeReg(M::CONFIG, 0xE2, 0x06);    // Mic preamp disabled, anti-pop enabled
+    writeReg(M::CONFIG, 0x34, 0x98);    // FM bpf enabled, 25kHz bandwidth
+    writeReg(M::CONFIG, 0x60, 0x00);    // Disable both analog and DMR transmission
+    writeReg(M::CONFIG, 0x1F, 0x00);    // Color code, encryption disabled
     writeReg(M::AUX,    0x24, 0x00);
     writeReg(M::AUX,    0x25, 0x00);
     writeReg(M::AUX,    0x26, 0x00);
     writeReg(M::AUX,    0x27, 0x00);
-    writeReg(M::CONFIG, 0x56, 0x00);
-    writeReg(M::CONFIG, 0x41, 0x40);
-    writeReg(M::CONFIG, 0x5C, 0x09);
-    writeReg(M::CONFIG, 0x5F, 0xC0);
+    writeReg(M::CONFIG, 0x56, 0x00);    // Undocumented register
+    writeReg(M::CONFIG, 0x41, 0x40);    // Start RX for upcoming time slot interrupt
+    writeReg(M::CONFIG, 0x5C, 0x09);    // Undocumented register
+    writeReg(M::CONFIG, 0x5F, 0xC0);    // Detect BS and MS frame sequences in 2 layer mode
     sendSequence(initSeq7, sizeof(initSeq7));
-    writeReg(M::CONFIG, 0x11, 0x80);
-    writeReg(M::CONFIG, 0xE0, 0xC9);
+    writeReg(M::CONFIG, 0x11, 0x80);    // Local channel mode
+    writeReg(M::CONFIG, 0xE0, 0xC9);    // Codec enabled, LineIn1, LineOut2, I2S slave mode
 
-    writeReg(M::CONFIG, 0x37, 0x81);
+    writeReg(M::CONFIG, 0x37, 0x81);    // DAC gain
 }
 
 template< class M >
@@ -204,43 +204,41 @@ void HR_Cx000< M >::startAnalogTx(const TxAudioSource source, const FmConfig cfg
     if(source == TxAudioSource::MIC)     audioCfg |= 0x40;
     if(source == TxAudioSource::LINE_IN) audioCfg |= 0x02;
 
-    writeReg(M::CONFIG, 0xE2, 0x00);
-    writeReg(M::CONFIG, 0xE4, 0x23);
-    writeReg(M::CONFIG, 0xC2, 0x00);
-    writeReg(M::CONFIG, 0xA1, 0x80);
-//     writeReg(M::CONFIG, 0x25, 0x0E);
-//     writeReg(M::CONFIG, 0x26, 0xFE);
-    writeReg(M::CONFIG, 0x83, 0xFF);
-    writeReg(M::CONFIG, 0x87, 0x00);
-    writeReg(M::CONFIG, 0x04, 0x24);
-    writeReg(M::CONFIG, 0x35, 0x40);
-    writeReg(M::CONFIG, 0x3F, 0x04);
+    writeReg(M::CONFIG, 0xE2, 0x00);    // Mic preamp disabled, anti-pop disabled
+    writeReg(M::CONFIG, 0xE4, 0x23);    // Lineout gain, first and second stage mic gain
+    writeReg(M::CONFIG, 0xC2, 0x00);    // Codec AGC gain
+    writeReg(M::CONFIG, 0xA1, 0x80);    // FM_mod, all modes cleared
+    writeReg(M::CONFIG, 0x83, 0xFF);    // Clear all interrupt flags
+    writeReg(M::CONFIG, 0x87, 0x00);    // Disable all interrupt sources
+//     writeReg(M::CONFIG, 0x04, 0x24);
+//     writeReg(M::CONFIG, 0x35, 0x40);
+//     writeReg(M::CONFIG, 0x3F, 0x04);
     writeReg(M::CONFIG, 0x34, static_cast< uint8_t >(cfg));
-    writeReg(M::CONFIG, 0x3E, 0x08);
+    writeReg(M::CONFIG, 0x3E, 0x08);    // FM Modulation frequency deviation coefficient at the receiving end
     writeReg(M::AUX,    0x50, 0x00);
     writeReg(M::AUX,    0x51, 0x00);
-    writeReg(M::CONFIG, 0x60, 0x80);
-    writeReg(M::CONFIG, 0x10, 0xF3);
+    writeReg(M::CONFIG, 0x60, 0x80);    // Start analog transmission
+    writeReg(M::CONFIG, 0x10, 0xF3);    // FM mode, Tier II, TimeSlot, 3rd layer mode, aligned (?)
 
     writeReg(M::CONFIG, 0xE0, audioCfg);
-    writeReg(M::CONFIG, 0x37, 0x8C);
+    writeReg(M::CONFIG, 0x37, 0x8C);    // DAC gain
 }
 
 template< class M >
 void HR_Cx000< M >::stopAnalogTx()
 {
-    writeReg(M::CONFIG, 0x60, 0x00);
-    writeReg(M::CONFIG, 0xE0, 0xC9);
-    writeReg(M::CONFIG, 0xE2, 0x06);
-    writeReg(M::CONFIG, 0x34, 0x98);
-    writeReg(M::CONFIG, 0x37, 0x81);
+    writeReg(M::CONFIG, 0x60, 0x00);    // Stop analog transmission
+    writeReg(M::CONFIG, 0xE0, 0xC9);    // Codec enabled, LineIn1, LineOut2, I2S slave mode
+    writeReg(M::CONFIG, 0xE2, 0x06);    // Mic preamp disabled, anti-pop enabled
+    writeReg(M::CONFIG, 0x34, 0x98);    // FM bpf enabled, 25kHz bandwidth
+    writeReg(M::CONFIG, 0x37, 0x81);    // DAC gain
 }
 
 /*
  * SPI interface driver
  */
 template< class M >
-void HR_Cx000<M>::uSpi_init()
+void HR_Cx000< M >::uSpi_init()
 {
     gpio_setMode(DMR_CS,    OUTPUT);
     gpio_setMode(DMR_CLK,   OUTPUT);
@@ -252,7 +250,7 @@ void HR_Cx000<M>::uSpi_init()
 }
 
 template< class M >
-uint8_t HR_Cx000<M>::uSpi_sendRecv(const uint8_t value)
+uint8_t HR_Cx000< M >::uSpi_sendRecv(const uint8_t value)
 {
     gpio_clearPin(DMR_CLK);