Commit Graph

9 Commits

Author SHA1 Message Date
Silvano Seva 4b8685b853 Changed gain and added an offset at tx RRC stage only for Module 17 to compensate for an hardware bug 2022-05-27 21:48:47 +02:00
Silvano Seva d1b4973cc9 Fixed reset of DC bias on stream stop in Module 17 output stream driver, made parametric the gain of the RRC at modulator side 2022-05-27 21:48:47 +02:00
Silvano Seva c9a4bfb199 Cleanup and refactoring of M17 modulator class, now using output streams for baseband signal output 2022-05-27 21:48:47 +02:00
Niccolò Izzo 2d8c696a09 Complete M17 demodulator implementation
Make quantization work also on DC offset signal
Add samples plot code
Fix bug in buffer wrap around
Fix oob memory access in M17 modulator
Update tests with DC offset signal
Switch to 48KHz sample rate for Module17 and MD380
Add DC biasing script

TG-81
2022-05-27 21:48:46 +02:00
Niccolò Izzo 3aeade6c1f Clarify M17 modulator constant naming
Further clarify modulator constant naming for sample rate and frame
lengths, to distinguish between demodulator values.
2022-05-27 21:48:46 +02:00
Niccolò Izzo 6588a6718e Add M17 namespace in M17 related source files
Now M17 source files reside in the M17 namespace, the OPMODE_ prefix
was added to all opmode enums to avoid a name clash.
2022-05-27 21:48:46 +02:00
Niccolò Izzo 876cb87d57 Move rrc filter into separate compilation unit
By moving the rrc filter into a separate compilation unit with its own
header file, we can use it both in the modulator and in the demodulator.
2022-05-27 21:48:46 +02:00
Silvano Seva a3b7b490d4 Fixed jitter in M17 baseband signal generation 2022-05-27 21:48:46 +02:00
Silvano Seva 39e41ee470 M17 4FSK modulator class 2021-09-03 16:44:57 +02:00