89 lines
3.4 KiB
C
89 lines
3.4 KiB
C
/***************************************************************************
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* Copyright (C) 2020 - 2025 by Silvano Seva IU2KWO *
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* and Niccolò Izzo IU2KIN *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include "interfaces/delays.h"
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#include <math.h>
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#include "drivers/baseband/SKY72310.h"
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static inline void writeReg(const struct sky73210 *dev, const uint16_t value)
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{
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const uint16_t tmp = __builtin_bswap16(value);
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/*
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* NOTE: for some (yet) unknown reason, there must be at least 10us between
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* chip select assertion/deassertion and the SPI transaction. For lower
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* values the PLL seems to go nuts.
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*/
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spi_acquire(dev->spi);
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gpioPin_clear(&dev->cs);
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delayUs(10);
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spi_send(dev->spi, &tmp, 2);
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delayUs(10);
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gpioPin_set(&dev->cs);
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spi_release(dev->spi);
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}
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void SKY73210_init(const struct sky73210 *dev)
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{
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gpioPin_setMode(&dev->cs, OUTPUT);
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gpioPin_set(&dev->cs);
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writeReg(dev, 0x6000 | 0x1F); // Phase detector gain
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writeReg(dev, 0x73D0); // Power down/multiplexer control register
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writeReg(dev, 0x8000); // Modulation control register
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writeReg(dev, 0x9000); // Modulation data register
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}
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void SKY73210_terminate(const struct sky73210 *dev)
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{
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(void) dev;
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}
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void SKY73210_setFrequency(const struct sky73210 *dev, const uint32_t freq,
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uint8_t clkDiv)
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{
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// Maximum allowable value for reference clock divider is 32
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if (clkDiv > 32)
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clkDiv = 32;
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float clk = ((float) dev->refClk) / ((float) clkDiv);
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float K = ((float) freq) / clk;
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float Ndiv = floor(K) - 32.0;
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float Ndnd = round(262144 * (K - Ndiv - 32.0));
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/*
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* With PLL in fractional mode, dividend range is [-131017 +131071].
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* When converting from float to uint32_t we have to cast the value to a
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* signed 18-bit one and increment the divider by one if dividend is negative.
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*/
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uint32_t dnd = ((uint32_t) Ndnd) & 0x03FFFF;
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if(dnd & 0x20000)
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Ndiv += 1;
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uint16_t dndMsb = dnd >> 8;
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uint16_t dndLsb = dnd & 0x00FF;
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writeReg(dev, (uint16_t) Ndiv); // Divider register
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writeReg(dev, 0x2000 | dndLsb); // Dividend LSB register
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writeReg(dev, 0x1000 | dndMsb); // Dividend MSB register
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writeReg(dev, 0x5000 | ((uint16_t)clkDiv - 1)); // Reference clock divider
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}
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