126 lines
4.3 KiB
C
126 lines
4.3 KiB
C
/***************************************************************************
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* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <hwconfig.h>
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#include <interfaces/gpio.h>
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#include <interfaces/delays.h>
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#include <interfaces/platform.h>
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#include <stdint.h>
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#include <string.h>
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#include <I2C0.h>
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#include "interfaces.h"
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/*
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* Implementation of AT1846S I2C interface.
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*
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* NOTE: on GDx devices the I2C bus is shared between the EEPROM and the AT1846S,
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* so we have to acquire exclusive ownership before exchanging data
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*/
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static const uint8_t devAddr = 0xE2;
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void i2c_init()
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{
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/* I2C already init'd by platform support package */
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}
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void i2c_writeReg16(uint8_t reg, uint16_t value)
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{
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/*
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* Beware of endianness!
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* When writing an AT1846S register, bits 15:8 must be sent first, followed
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* by bits 7:0.
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*/
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uint8_t buf[3];
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buf[0] = reg;
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buf[1] = (value >> 8) & 0xFF;
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buf[2] = value & 0xFF;
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i2c0_lockDeviceBlocking();
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i2c0_write(devAddr, buf, 3, true);
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i2c0_releaseDevice();
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}
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uint16_t i2c_readReg16(uint8_t reg)
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{
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uint16_t value = 0;
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i2c0_lockDeviceBlocking();
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i2c0_write(devAddr, ®, 1, false);
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i2c0_read(devAddr, &value, 2);
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i2c0_releaseDevice();
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/* Correction for AT1846S sending register data in big endian format */
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return __builtin_bswap16(value);
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}
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/*
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* Implementation of HR_C6000 "user" SPI interface.
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*/
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void uSpi_init()
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{
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gpio_setMode(DMR_CLK, OUTPUT);
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gpio_setMode(DMR_MOSI, OUTPUT);
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gpio_setMode(DMR_MISO, INPUT);
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gpio_setAlternateFunction(DMR_CLK, 0);
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gpio_setAlternateFunction(DMR_MOSI, 0);
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gpio_setAlternateFunction(DMR_MISO, 0);
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SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
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SPI0->MCR &= ~SPI_MCR_MDIS_MASK; /* Enable the SPI0 module */
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SPI0->MCR |= SPI_MCR_MSTR_MASK /* Master mode */
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| SPI_MCR_PCSIS_MASK /* CS high when inactive */
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| SPI_MCR_DIS_RXF_MASK /* Disable RX FIFO */
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| SPI_MCR_DIS_TXF_MASK /* Disable TX FIFO */
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| SPI_MCR_HALT_MASK; /* Stop transfers */
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SPI0->CTAR[0] = SPI_CTAR_FMSZ(7) /* 8bit frame size */
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| SPI_CTAR_CPHA_MASK /* CPHA = 1 */
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| SPI_CTAR_PBR(2) /* CLK prescaler divide by 5 */
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| SPI_CTAR_BR(3) /* CLK scaler divide by 8 */
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| SPI_CTAR_PCSSCK(1)
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| SPI_CTAR_PASC(1)
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| SPI_CTAR_CSSCK(4)
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| SPI_CTAR_ASC(4);
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}
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uint8_t uSpi_sendRecv(uint8_t val)
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{
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SPI0->MCR &= ~SPI_MCR_HALT_MASK; /* Start transfer */
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SPI0->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK;
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while((SPI0->SR & SPI_SR_TFFF_MASK) == 0) ;
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SPI0->PUSHR = SPI_PUSHR_EOQ_MASK | val;
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SPI0->SR |= SPI_SR_TFFF_MASK;
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while((SPI0->SR & SPI_SR_RFDF_MASK) == 0) ;
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SPI0->SR |= SPI_SR_RFDF_MASK;
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SPI0->MCR |= SPI_MCR_HALT_MASK; /* Start transfer */
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return SPI0->POPR;
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}
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