112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/***************************************************************************
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* Copyright (C) 2020 by Silvano Seva IU2KWO and Niccolò Izzo IU2KIN *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include "pll_MD3x0.h"
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#include <math.h>
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#include "gpio.h"
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#include "delays.h"
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#include "hwconfig.h"
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#define REF_CLK 16800000.0F /* Reference clock: 16.8MHz */
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#define PHD_GAIN 0x1F /* Phase detector gain: hex value, max 0x1F */
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void _spiSend(uint16_t value)
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{
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uint16_t temp = value;
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gpio_clearPin(PLL_CS);
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delayUs(10);
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for(uint8_t i = 0; i < 16; i++)
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{
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gpio_setPin(PLL_CLK);
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delayUs(1);
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if(temp & 0x8000)
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{
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gpio_setPin(PLL_DAT);
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}
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else
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{
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gpio_clearPin(PLL_DAT);
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}
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temp <<= 1;
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delayUs(1);
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gpio_clearPin(PLL_CLK);
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delayUs(1);
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}
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gpio_setPin(PLL_CLK);
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delayUs(10);
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gpio_setPin(PLL_CS);
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}
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void pll_init()
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{
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gpio_setMode(PLL_CLK, OUTPUT);
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gpio_setMode(PLL_DAT, OUTPUT);
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gpio_setMode(PLL_CS, OUTPUT);
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gpio_setPin(PLL_CS);
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gpio_setMode(PLL_LD, INPUT);
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_spiSend(0x6000 | ((uint16_t) PHD_GAIN)); /* Phase detector gain */
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_spiSend(0x73D0); /* Power down/multiplexer control register */
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_spiSend(0x8000); /* Modulation control register */
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_spiSend(0x9000); /* Modulation data register */
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}
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void pll_terminate()
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{
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gpio_setMode(PLL_CLK, INPUT);
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gpio_setMode(PLL_DAT, INPUT);
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gpio_setMode(PLL_CS, INPUT);
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}
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void pll_setFrequency(float freq, uint8_t clkDiv)
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{
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/* Maximum allowable value for reference clock divider is 32 */
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if (clkDiv > 32) clkDiv = 32;
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float K = freq/(REF_CLK/((float) clkDiv));
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float Ndiv = floor(K) - 32.0;
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float Ndnd = round(262144*(K - Ndiv - 32.0));
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uint32_t dnd = ((uint32_t) Ndnd);
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uint16_t dndMsb = dnd >> 8;
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uint16_t dndLsb = dnd & 0x00FF;
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_spiSend((uint16_t) Ndiv); /* Divider register */
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_spiSend(0x2000 | dndLsb); /* Dividend LSB register */
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_spiSend(0x1000 | dndMsb); /* Dividend MSB register */
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_spiSend(0x5000 | ((uint16_t)clkDiv - 1)); /* Reference clock divider */
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}
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bool pll_locked()
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{
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return (gpio_readPin(PLL_LD) == 1) ? true : false;
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}
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bool pll_spiInUse()
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{
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/* If PLL chip select is low, SPI is being used by this driver. */
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return (gpio_readPin(PLL_CS) == 1) ? false : true;
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}
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