296 lines
12 KiB
C++
296 lines
12 KiB
C++
/***************************************************************************
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* Copyright (C) 2010-2018 by Terraneo Federico *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* As a special exception, if other files instantiate templates or use *
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* macros or inline functions from this file, or you compile this file *
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* and link it with other works to produce a work based on this file, *
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* this file does not by itself cause the resulting work to be covered *
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* by the GNU General Public License. However the source code for this *
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* file must still be made available in accordance with the GNU General *
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* Public License. This exception does not invalidate any other reasons *
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* why a work based on this file might be covered by the GNU General *
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* Public License. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#ifndef SERIAL_STM32_H
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#define SERIAL_STM32_H
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#include "filesystem/console/console_device.h"
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#include "kernel/sync.h"
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#include "kernel/queue.h"
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#include "interfaces/gpio.h"
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#include "board_settings.h"
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#if defined(_ARCH_CORTEXM3_STM32) && defined(__ENABLE_XRAM)
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//Quirk: concurrent access to the FSMC from both core and DMA is broken in
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//the stm32f1, so disable DMA mode if XRAM is enabled.
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#undef SERIAL_1_DMA
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#undef SERIAL_2_DMA
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#undef SERIAL_3_DMA
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#endif
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#if defined(SERIAL_1_DMA) || defined(SERIAL_2_DMA) || defined(SERIAL_3_DMA)
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#define SERIAL_DMA
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#endif
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#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32)
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#undef SERIAL_1_DMA
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#undef SERIAL_2_DMA
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#undef SERIAL_3_DMA
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#undef SERIAL_DMA
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#warning "DMA not yet implemented for STM32F0 family"
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#endif
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namespace miosix {
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/**
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* Serial port class for stm32 microcontrollers.
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* Only supports USART1, USART2 and USART3
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* Additionally, USARTx can use DMA if SERIAL_x_DMA is defined in
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* board_settings.h, while the other serial use polling for transmission,
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* and interrupt for reception.
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*
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* Classes of this type are reference counted, must be allocated on the heap
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* and managed through intrusive_ref_ptr<FileBase>
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*/
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class STM32Serial : public Device
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{
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public:
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enum FlowCtrl
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{
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NOFLOWCTRL, ///< No hardware flow control
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RTSCTS ///< RTS/CTS hardware flow control
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};
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/**
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* Constructor, initializes the serial port using the default pins, which
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* are:
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* USART1: tx=PA9 rx=PA10 cts=PA11 rts=PA12
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* USART2: tx=PA2 rx=PA3 cts=PA0 rts=PA1
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* USART3: tx=PB10 rx=PB11 cts=PB13 rts=PB14
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* If you board has a different mapping, use one of the other constructors.
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*
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* Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when
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* attempting to construct multiple objects with the same id. That is,
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* it is possible to instantiate only one instance of this class for each
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* hardware USART.
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* \param id a number 1 to 3 to select which USART
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* \param baudrate serial port baudrate
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* \param flowControl to enable hardware flow control on this port
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*/
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STM32Serial(int id, int baudrate, FlowCtrl flowControl=NOFLOWCTRL);
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/**
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* Constructor, initializes the serial port using remapped pins and disables
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* flow control.
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*
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* NOTE: for stm32f2, f4, f7 and h7 you have to set the correct alternate
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* function to the pins in order to connect then to the USART peripheral
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* before passing them to this class.
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*
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* Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when
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* attempting to construct multiple objects with the same id. That is,
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* it is possible to instantiate only one instance of this class for each
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* hardware USART.
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* \param id a number 1 to 3 to select which USART
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* \param baudrate serial port baudrate
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* \param tx tx pin
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* \param rx rx pin
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*/
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STM32Serial(int id, int baudrate, miosix::GpioPin tx, miosix::GpioPin rx);
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/**
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* Constructor, initializes the serial port using remapped pins and enables
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* flow control.
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*
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* NOTE: for stm32f2, f4, f7 and h7 you have to set the correct alternate
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* function to the pins in order to connect then to the USART peripheral
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* before passing them to this class.
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*
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* Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when
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* attempting to construct multiple objects with the same id. That is,
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* it is possible to instantiate only one instance of this class for each
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* hardware USART.
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* \param id a number 1 to 3 to select which USART
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* \param tx tx pin
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* \param rx rx pin
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* \param rts rts pin
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* \param cts cts pin
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*/
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STM32Serial(int id, int baudrate, miosix::GpioPin tx, miosix::GpioPin rx,
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miosix::GpioPin rts, miosix::GpioPin cts);
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/**
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* Read a block of data
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* \param buffer buffer where read data will be stored
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* \param size buffer size
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* \param where where to read from
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* \return number of bytes read or a negative number on failure. Note that
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* it is normal for this function to return less character than the amount
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* asked
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*/
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ssize_t readBlock(void *buffer, size_t size, off_t where);
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/**
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* Write a block of data
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* \param buffer buffer where take data to write
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* \param size buffer size
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* \param where where to write to
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* \return number of bytes written or a negative number on failure
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*/
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ssize_t writeBlock(const void *buffer, size_t size, off_t where);
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/**
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* Write a string.
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* An extension to the Device interface that adds a new member function,
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* which is used by the kernel on console devices to write debug information
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* before the kernel is started or in case of serious errors, right before
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* rebooting.
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* Can ONLY be called when the kernel is not yet started, paused or within
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* an interrupt. This default implementation ignores writes.
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* \param str the string to write. The string must be NUL terminated.
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*/
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void IRQwrite(const char *str);
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/**
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* Performs device-specific operations
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* \param cmd specifies the operation to perform
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* \param arg optional argument that some operation require
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* \return the exact return value depends on CMD, -1 is returned on error
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*/
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int ioctl(int cmd, void *arg);
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/**
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* \internal the serial port interrupts call this member function.
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* Never call this from user code.
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*/
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void IRQhandleInterrupt();
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#ifdef SERIAL_DMA
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/**
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* \internal the serial port DMA tx interrupts call this member function.
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* Never call this from user code.
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*/
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void IRQhandleDMAtx();
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/**
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* \internal the serial port DMA rx interrupts call this member function.
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* Never call this from user code.
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*/
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void IRQhandleDMArx();
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#endif //SERIAL_DMA
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/**
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* \return port id, 1 for USART1, 2 for USART2, ...
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*/
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int getId() const { return portId; }
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/**
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* Destructor
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*/
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~STM32Serial();
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private:
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/**
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* Code common for all constructors
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*/
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void commonInit(int id, int baudrate, miosix::GpioPin tx, miosix::GpioPin rx,
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miosix::GpioPin rts, miosix::GpioPin cts);
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#ifdef SERIAL_DMA
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/**
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* Wait until a pending DMA TX completes, if any
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*/
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void waitDmaTxCompletion();
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/**
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* Write to the serial port using DMA. When the function returns, the DMA
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* transfer is still in progress.
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* \param buffer buffer to write
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* \param size size of buffer to write
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*/
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void writeDma(const char *buffer, size_t size);
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/**
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* Read from DMA buffer and write data to queue
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*/
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void IRQreadDma();
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/**
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* Start DMA read
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*/
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void IRQdmaReadStart();
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/**
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* Stop DMA read
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* \return the number of characters in rxBuffer
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*/
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int IRQdmaReadStop();
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#endif //SERIAL_DMA
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/**
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* Wait until all characters have been written to the serial port.
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* Needs to be callable from interrupts disabled (it is used in IRQwrite)
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*/
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void waitSerialTxFifoEmpty()
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{
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#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
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&& !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
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&& !defined(_ARCH_CORTEXM4_STM32L4)
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while((port->SR & USART_SR_TC)==0) ;
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#else //_ARCH_CORTEXM7_STM32F7/H7
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while((port->ISR & USART_ISR_TC)==0) ;
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#endif //_ARCH_CORTEXM7_STM32F7/H7
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}
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FastMutex txMutex; ///< Mutex locked during transmission
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FastMutex rxMutex; ///< Mutex locked during reception
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DynUnsyncQueue<char> rxQueue; ///< Receiving queue
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static const unsigned int rxQueueMin=16; ///< Minimum queue size
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Thread *rxWaiting=0; ///< Thread waiting for rx, or 0
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USART_TypeDef *port; ///< Pointer to USART peripheral
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#ifdef SERIAL_DMA
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#if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
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|| defined(_ARCH_CORTEXM4_STM32L4)
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DMA_Channel_TypeDef *dmaTx; ///< Pointer to DMA TX peripheral
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DMA_Channel_TypeDef *dmaRx; ///< Pointer to DMA RX peripheral
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#else //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
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DMA_Stream_TypeDef *dmaTx; ///< Pointer to DMA TX peripheral
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DMA_Stream_TypeDef *dmaRx; ///< Pointer to DMA RX peripheral
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#endif //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
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Thread *txWaiting; ///< Thread waiting for tx, or 0
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static const unsigned int txBufferSize=16; ///< Size of tx buffer, for tx speedup
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/// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the
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/// STM32F4, as it is used to perform DMA operations. This is guaranteed by
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/// the fact that this class must be allocated on the heap as it derives
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/// from Device, and the Miosix linker scripts never put the heap in CCM
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char txBuffer[txBufferSize];
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/// This buffer emulates the behaviour of a 16550. It is filled using DMA
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/// and an interrupt is fired as soon as it is half full
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char rxBuffer[rxQueueMin];
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bool dmaTxInProgress; ///< True if a DMA tx is in progress
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#endif //SERIAL_DMA
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bool idle=true; ///< Receiver idle
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const bool flowControl; ///< True if flow control GPIOs enabled
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const unsigned char portId; ///< 1 for USART1, 2 for USART2, ...
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};
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} //namespace miosix
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#endif //SERIAL_STM32_H
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