131 lines
4.0 KiB
C++
131 lines
4.0 KiB
C++
/***************************************************************************
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* Copyright (C) 2017 by Matteo Michele Piazzolla *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* As a special exception, if other files instantiate templates or use *
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* macros or inline functions from this file, or you compile this file *
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* and link it with other works to produce a work based on this file, *
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* this file does not by itself cause the resulting work to be covered *
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* by the GNU General Public License. However the source code for this *
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* file must still be made available in accordance with the GNU General *
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* Public License. This exception does not invalidate any other reasons *
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* why a work based on this file might be covered by the GNU General *
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* Public License. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include "board_settings.h"
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#include "stm32_sgm.h"
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#include <string.h>
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#include "miosix.h"
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namespace miosix {
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extern unsigned char _preserve_start asm("_preserve_start");
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extern unsigned char _preserve_end asm("_preserve_end");
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static unsigned char *preserve_start=&_preserve_start;
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static unsigned char *preserve_end=&_preserve_end;
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SGM& SGM::instance()
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{
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static SGM singleton;
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return singleton;
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}
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SGM::SGM()
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{
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/* Enable PWR clock */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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/* Enable backup SRAM Clock */
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RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
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enableWrite();
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/* Enable Backup regulator */
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PWR->CSR |= PWR_CSR_BRE;
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/* Enable the Backup SRAM low power Regulator */
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PWR->CSR |= PWR_CSR_BRE;
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/* Wait for backup regulator */
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while (!(PWR->CSR & (PWR_CSR_BRR)));
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/* Retrive last reset reason and clear the pending flag */
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readResetRegister();
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/*
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* If the reset wasn't caused by software failure we cannot trust
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* the content of the backup memory and we need to clear it.
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*/
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if(lastReset != RST_SW)
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{
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memset(preserve_start, 0, preserve_end-preserve_start);
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}
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}
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void SGM::disableWrite()
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{
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/* Enable Backup Domain write protection */
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PWR->CR &= ~PWR_CR_DBP;
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}
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void SGM::enableWrite()
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{
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/* Disable Backup Domain write protection */
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PWR->CR |= PWR_CR_DBP;
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}
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void SGM::clearResetFlag()
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{
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RCC->CSR |= RCC_CSR_RMVF;
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}
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void SGM::readResetRegister()
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{
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uint32_t resetReg = RCC->CSR;
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clearResetFlag();
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if(resetReg & RCC_CSR_LPWRRSTF)
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{
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lastReset = RST_LOW_PWR;
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}
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else if( resetReg & RCC_CSR_WWDGRSTF)
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{
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lastReset = RST_WINDOW_WDG;
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}
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else if( resetReg & RCC_CSR_WDGRSTF)
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{
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lastReset = RST_INDEPENDENT_WDG;
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}
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else if( resetReg & RCC_CSR_SFTRSTF)
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{
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lastReset = RST_SW;
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}
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else if( resetReg & RCC_CSR_PORRSTF)
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{
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lastReset = RST_POWER_ON;
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}
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else if( resetReg & RCC_CSR_PADRSTF)
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{
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lastReset = RST_PIN;
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}
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else
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{
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lastReset = RST_UNKNOWN;
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}
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}
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} // namespace miosix
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