132 lines
4.0 KiB
C
132 lines
4.0 KiB
C
/***************************************************************************
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* Copyright (C) 2024 by Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <stm32h7xx.h>
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#include <pthread.h>
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#include <errno.h>
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#include "adc_stm32.h"
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int adcStm32_init(const struct Adc *adc)
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{
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/*
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* Configure ADC for synchronous clock mode (clocked by AHB clock), divided
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* by 4. This gives an ADC clock of 50MHz when AHB clock is 200MHz.
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*
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* NOTE: ADC1 and ADC2 share the same clock tree!
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*/
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switch((uint32_t) adc->priv)
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{
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case ADC1_BASE:
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case ADC2_BASE:
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RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN;
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__DSB();
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ADC12_COMMON->CCR = ADC_CCR_CKMODE_1
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| ADC_CCR_CKMODE_0;
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break;
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case ADC3_BASE:
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RCC->AHB4ENR |= RCC_AHB4ENR_ADC3EN;
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__DSB();
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ADC3_COMMON->CCR = ADC_CCR_CKMODE_1
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| ADC_CCR_CKMODE_0;
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break;
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default:
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return -EINVAL;
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break;
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}
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ADC_TypeDef *pAdc = ((ADC_TypeDef *) adc->priv);
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// Enable ADC voltage regulator, enable boost mode. Wait until LDO regulator
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// is ready.
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pAdc->CR = ADC_CR_ADVREGEN
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| ADC_CR_BOOST_1
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| ADC_CR_BOOST_0;
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while((pAdc->ISR & ADC_ISR_LDORDY) == 0) ;
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// Start calibration, both offset and linearity.
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pAdc->CR |= ADC_CR_ADCAL
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| ADC_CR_ADCALLIN;
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while((pAdc->CR & ADC_CR_ADCAL) != 0) ;
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/*
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* ADC clock is 50MHz. We set the sample time of each channel to 387.5 ADC
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* cycles, giving a total conversion time of ~7us.
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*/
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pAdc->SMPR2 = 0x36DB6DB6;
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pAdc->SMPR1 = 0x36DB6DB6;
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// Finally,turn on the ADC
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pAdc->CR |= ADC_CR_ADEN;
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while((pAdc->ISR & ADC_ISR_ADRDY) != 0) ;
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if(adc->mutex != NULL)
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pthread_mutex_init((pthread_mutex_t *) adc->mutex, NULL);
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return 0;
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}
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void adcStm32_terminate(const struct Adc *adc)
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{
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// A conversion may be in progress, wait until it finishes
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if(adc->mutex != NULL)
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pthread_mutex_lock((pthread_mutex_t *) adc->mutex);
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((ADC_TypeDef *) adc->priv)->CR = 0;
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switch((uint32_t) adc->priv)
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{
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case ADC1_BASE:
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case ADC2_BASE:
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if((ADC1->CR == 0) && (ADC2->CR == 0))
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RCC->AHB1ENR &= ~RCC_AHB1ENR_ADC12EN;
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__DSB();
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break;
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case ADC3_BASE:
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RCC->AHB4ENR &= ~RCC_AHB4ENR_ADC3EN;
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__DSB();
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break;
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default:
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break;
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}
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if(adc->mutex != NULL)
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pthread_mutex_destroy((pthread_mutex_t *) adc->mutex);
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}
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uint16_t adcStm32_sample(const struct Adc *adc, const uint32_t channel)
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{
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if(channel > 16)
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return 0;
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ADC_TypeDef *pAdc = ((ADC_TypeDef *) adc->priv);
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pAdc->SQR1 = channel << ADC_SQR1_SQ1_Pos;
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pAdc->PCSEL = 1 << channel;
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pAdc->CR |= ADC_CR_ADSTART;
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while((pAdc->ISR & ADC_ISR_EOC) == 0) ;
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return pAdc->DR;
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}
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