Optimized wiring.c changed bootloader combo
Optimized wiring.c assembly code Changed bootloader trigger combo to press UP + DOWN for ~1.5 seconds removed turning on Rx LED when bootloader combo is triggered removed bootloader trigger wait for button release
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Mr.Blinky
GitHub
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0de4b41588
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a76f43a053
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@ -125,39 +125,23 @@ ISR(TIMER0_OVF_vect, ISR_NAKED)
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" cpse r24, r1 \n\t" //if (buttons) button_ticks_last = (uint8_t)(Millis >> 12)
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" sts %[apd], r16 \n\t"
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#ifdef AB_DEVKIT
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" cpi r24, 0x33 \n\t" // test LEFT+UP+A+B for bootloader
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" breq 2f \n\t"
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" cpi r24, 0x47 \n\t" // test RIGHT+DOWN+A+B for reset sketch
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" brne 5f \n\t"
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" cpi r24, 0x50 \n\t" // test DevKit UP+DOWN for bootloader
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#else
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" cpi r24, 0xAC \n\t" // test LEFT+UP+A+B for bootloader
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" breq 2f \n\t"
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" cpi r24, 0x5C \n\t" // test RIGHT+DOWN+A+B for reset sketch
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" brne 5f \n\t"
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" cpi r24, 0x90 \n\t" // test arduboy UP+DOWN for bootloader
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#endif
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" brne 5f \n\t"
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"2: lds r16, %[hold] \n\t"
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" sub r25, r16 \n\t" // (uint8_t)(timer0_millis >> 6) - button_ticks_last
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" sub r25, r16 \n\t" // (uint8_t)(timer0_millis >> 8) - button_ticks_last
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" cpi r25, 6 \n\t"
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" brcs 6f \n\t" // if ((millis - hold) < 6)
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#ifdef AB_DEVKIT
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" subi r24, 0x33 - 0x77 \n\t" //get bootloader key or reset key value
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#else
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" subi r24, 0xAC - 0x77 \n\t" //get bootloader key or reset key value
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#endif
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"3: sts 0x800, r24 \n\t"
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" brcs 6f \n\t" // if ((millis - hold) >= 6) {
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"3: ldi r24, 0x77 \n\t"
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" sts 0x800, r24 \n\t"
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" sts 0x801, r24 \n\t"
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#ifndef ARDUINO_AVR_MICRO
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" cbi %[led_port], %[led_bit] \n\t" //light up LED to acknowledge bootloader or reset is triggered
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#else
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" sbi %[led_port], %[led_bit] \n\t"
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#endif
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"4: rcall scan_buttons \n\t" //wait for buttons to be released
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" brne 4b \n\t"
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" ldi r24, %[value1] \n\t"
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" ldi r25, %[value2] \n\t"
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" sts %[wdtcsr], r24 \n\t"
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" sts %[wdtcsr], r25 \n\t"
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" rjmp .-2 \n\t"
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" rjmp .-2 \n\t" // }
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"5: \n\t"
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" sts %[hold], r25 \n\t" //button_ticks_hold = (uint8_t)(Millis >> 8)
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"6: \n\t"
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@ -165,15 +149,12 @@ ISR(TIMER0_OVF_vect, ISR_NAKED)
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" subi r24, 1 \n\t"
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" brcs 7f \n\t"
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" sts %[btimer],r24 \n\t"
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" ldi r24, 0x77 \n\t"
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" breq 3b \n\t" // if (bootloader_timer == 0) runBootLoader;
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"7: \n\t" //}
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:
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: [hold] "" (&button_ticks_hold),
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[apd] "" (&button_ticks_last),
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[btimer] "" (&bootloader_timer),
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[led_port] "M" (_SFR_IO_ADDR(PORTB)), //RX LED
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[led_bit] "M" (0),
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[value1] "M" ((uint8_t)(_BV(WDCE) | _BV(WDE))),
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[value2] "M" ((uint8_t)(_BV(WDE))),
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[wdtcsr] "M" (_SFR_MEM_ADDR(WDTCSR))
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@ -552,15 +533,11 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR0A, WGM01);
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//sbi(TCCR0A, WGM00);
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asm volatile(
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" in r24, %[tccr0a] \n\t"
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" ori r24, %[wgm01] \n\t"
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" out %[tccr0a], r24 \n\t"
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" ori r24, %[wgm00] \n\t"
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" ldi r24, %[value] \n\t"
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" out %[tccr0a], r24 \n\t"
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:
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: [tccr0a] "I" (_SFR_IO_ADDR(TCCR0A)),
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[wgm01] "M" (_BV(WGM01)),
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[wgm00] "M" (_BV(WGM00))
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[value] "M" (_BV(WGM01) | _BV(WGM00))
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: "r24"
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);
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#endif
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@ -578,15 +555,11 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR0B, CS01);
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//sbi(TCCR0B, CS00);
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asm volatile(
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" in r24, %[tccr0b] \n\t"
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" ori r24, %[cs01] \n\t"
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" out %[tccr0b], r24 \n\t"
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" ori r24, %[cs00] \n\t"
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" ldi r24, %[value] \n\t"
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" out %[tccr0b], r24 \n\t"
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:
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: [tccr0b] "I" (_SFR_IO_ADDR(TCCR0B)),
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[cs01] "M" (_BV(CS01)),
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[cs00] "M" (_BV(CS00))
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[value] "M" (_BV(CS01) | _BV(CS00))
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: "r24"
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);
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#elif defined(TCCR0A) && defined(CS01) && defined(CS00)
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@ -616,28 +589,24 @@ void init() //assembly optimized by 68 bytes
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// set timer 1 prescale factor to 64
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//sbi(TCCR1B, CS11);
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//#if F_CPU >= 8000000L
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//sbi(TCCR1B, CS10);
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//#endif
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asm volatile(
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" ldi r30, %[tccr1b] \n\t"
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" ldi r31, 0x00 \n\t"
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" st z, r1 \n\t"
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" ldi r24, %[cs11] \n\t"
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" ldi r24, %[value] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr1b] "M" (_SFR_MEM_ADDR(TCCR1B)),
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[cs11] "M" (_BV(CS11))
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: "r24", "r30", "r31"
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);
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#if F_CPU >= 8000000L
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//sbi(TCCR1B, CS10);
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asm volatile(
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" ori r24, %[cs10] \n\t"
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" st z, r24 \n\t"
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:
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: [cs10] "M" (_BV(CS10))
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[value] "M" (_BV(CS11) | _BV(CS10))
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#else
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[value] "M" (_BV(CS11))
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#endif
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: "r24", "r30", "r31"
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);
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#endif
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#elif defined(TCCR1) && defined(CS11) && defined(CS10)
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sbi(TCCR1, CS11);
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#if F_CPU >= 8000000L
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@ -649,8 +618,7 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR1A, WGM10);
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asm volatile(
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" ldi r30, %[tccr1a] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[wgm10] \n\t"
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" ldi r24, %[wgm10] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr1a] "M" (_SFR_MEM_ADDR(TCCR1A)),
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@ -682,22 +650,17 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR3B, CS30);
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asm volatile(
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" ldi r30, %[tccr3b] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[cs31] \n\t"
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" st z, r24 \n\t"
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" ori r24, %[cs30] \n\t"
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" ldi r24, %[value] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr3b] "M" (_SFR_MEM_ADDR(TCCR3B)),
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[cs31] "M" (_BV(CS31)),
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[cs30] "M" (_BV(CS30))
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[value] "M" (_BV(CS31) | _BV(CS30))
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: "r24", "r30", "r31"
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);
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//sbi(TCCR3A, WGM30); // put timer 3 in 8-bit phase correct pwm mode
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asm volatile(
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" ldi r30, %[tccr3a] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[wgm30] \n\t"
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" ldi r24, %[wgm30] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr3a] "M" (_SFR_MEM_ADDR(TCCR3A)),
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@ -712,25 +675,17 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR4B, CS40);
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asm volatile(
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" ldi r30, %[tccr4b] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[cs42] \n\t"
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" st z, r24 \n\t"
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" ori r24, %[cs41] \n\t"
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" st z, r24 \n\t"
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" ori r24, %[cs40] \n\t"
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" ldi r24, %[value] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr4b] "M" (_SFR_MEM_ADDR(TCCR4B)),
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[cs42] "M" (_BV(CS42)),
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[cs41] "M" (_BV(CS41)),
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[cs40] "M" (_BV(CS40))
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[value] "M" (_BV(CS42) | _BV(CS41) | _BV(CS40))
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: "r24", "r30", "r31"
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);
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//sbi(TCCR4D, WGM40); // put timer 4 in phase- and frequency-correct PWM mode
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asm volatile(
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" ldi r30, %[tccr4d] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[wgm40] \n\t"
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" ldi r24, %[wgm40] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr4d] "M" (_SFR_MEM_ADDR(TCCR4D)),
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@ -740,8 +695,7 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR4A, PWM4A); // enable PWM mode for comparator OCR4A
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asm volatile(
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" ldi r30, %[tccr4a] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[pwm4a] \n\t"
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" ldi r24, %[pwm4a] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr4a] "M" (_SFR_MEM_ADDR(TCCR4A)),
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@ -751,12 +705,11 @@ void init() //assembly optimized by 68 bytes
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//sbi(TCCR4C, PWM4D); // enable PWM mode for comparator OCR4D
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asm volatile(
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" ldi r30, %[tccr4c] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[pwm4d] \n\t"
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" ldi r24, %[value] \n\t"
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" st z, r24 \n\t"
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:
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: [tccr4c] "M" (_SFR_MEM_ADDR(TCCR4C)),
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[pwm4d] "M" (_BV(PWM4D))
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[value] "M" (_BV(PWM4D))
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: "r24", "r30", "r31"
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);
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#else /* beginning of timer4 block for ATMEGA1280 and ATMEGA2560 */
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@ -781,19 +734,12 @@ void init() //assembly optimized by 68 bytes
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//sbi(ADCSRA, ADPS0);
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asm volatile(
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" ldi r30, %[adcsra] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[adps2] \n\t"
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" st z, r24 \n\t"
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" ori r24, %[adps1] \n\t"
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" st z, r24 \n\t"
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" ori r24, %[adps0] \n\t"
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" ldi r24, %[value] \n\t"
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" st z, r24 \n\t"
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:
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: [adcsra] "M" (_SFR_MEM_ADDR(ADCSRA)),
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[adps2] "M" (_BV(ADPS2)),
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[adps1] "M" (_BV(ADPS1)),
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[adps0] "M" (_BV(ADPS0))
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: "r24", "r30", "r31"
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[value] "M" (_BV(ADPS2) |_BV(ADPS1) | _BV(ADPS0))
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: "r24"
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);
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#elif F_CPU >= 8000000 // 8 MHz / 64 = 125 KHz
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//sbi(ADCSRA, ADPS2);
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@ -801,18 +747,11 @@ void init() //assembly optimized by 68 bytes
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//cbi(ADCSRA, ADPS0);
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asm volatile(
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" ldi r30, %[adcsra] \n\t"
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" ld r24, z \n\t"
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" ori r24, %[adps2] \n\t"
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" st z, r24 \n\t"
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" ori r24, %[adps1] \n\t"
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" st z, r24 \n\t"
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" andi r24, %[adps0] \n\t"
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" ldi r24, %[value] \n\t"
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" st z, r24 \n\t"
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:
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: [adcsra] "M" (_SFR_MEM_ADDR(ADCSRA)),
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[adps2] "M" (_BV(ADPS2)),
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[adps1] "M" (_BV(ADPS1)),
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[adps0] "M" (~_BV(ADPS0))
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[value] "M" (_BV(ADPS2) | _BV(ADPS1))
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: "r24", "r30", "r31"
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);
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#elif F_CPU >= 4000000 // 4 MHz / 32 = 125 KHz
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