748 lines
26 KiB
C
748 lines
26 KiB
C
/*
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wiring.c - Partial implementation of the Wiring API for the ATmega8.
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Part of Arduino - http://www.arduino.cc/
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Copyright (c) 2005-2006 David A. Mellis
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General
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Public License along with this library; if not, write to the
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Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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Boston, MA 02111-1307 USA
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*/
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#include "wiring_private.h"
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// the prescaler is set so that timer0 ticks every 64 clock cycles, and the
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// the overflow handler is called every 256 ticks.
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#define MICROSECONDS_PER_TIMER0_OVERFLOW (clockCyclesToMicroseconds(64 * 256))
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// the whole number of milliseconds per timer0 overflow
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#define MILLIS_INC (MICROSECONDS_PER_TIMER0_OVERFLOW / 1000)
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// the fractional number of milliseconds per timer0 overflow. we shift right
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// by three to fit these numbers into a byte. (for the clock speeds we care
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// about - 8 and 16 MHz - this doesn't lose precision.)
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#define FRACT_INC ((MICROSECONDS_PER_TIMER0_OVERFLOW % 1000) >> 3)
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#define FRACT_MAX (1000 >> 3)
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volatile unsigned long timer0_overflow_count = 0;
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volatile unsigned long timer0_millis = 0;
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static unsigned char timer0_fract = 0;
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volatile unsigned char button_ticks_hold = 0;
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#if defined(TIM0_OVF_vect)
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ISR(TIM0_OVF_vect, ISR_NAKED)
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#else
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ISR(TIMER0_OVF_vect, ISR_NAKED)
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#endif
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{
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/*
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// copy these to local variables so they can be stored in registers
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// (volatile variables must be read from memory on every access)
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unsigned long m = timer0_millis;
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unsigned char f = timer0_fract;
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m += MILLIS_INC;
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f += FRACT_INC;
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if (f >= FRACT_MAX) {
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f -= FRACT_MAX;
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m += 1;
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}
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timer0_fract = f;
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timer0_millis = m;
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timer0_overflow_count++;
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assembly optimisation saves 50 bytes compared to compiled C++ version (148 bytes)
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with 28 bytes button code and 22 bytes exit to bootloader code, we end up with the
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same size but a cool feature added and 3 bytes ram saved (1 byte used extra for
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button_ticks_hold but 4 bytes saved due to less stack pushes)
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*/
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asm volatile(
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// save registers and SREG before 12622 after 12576 (saving 46 bytes)
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" push r0 \n"
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" in r0, __SREG__ \n"
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" push r24 \n"
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" push r25 \n"
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" push r30 \n"
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" push r31 \n" // millis_inc = MILLIS_INC; (MILLIS_INC == 1)
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" lds r24, %[fract] \n" // f= timer0_fract;
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" subi r24, - %[fract_inc] \n" // f += FRACT_INC;
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" cpi r24, %[fract_max] \n" // if (f >= FRACT_MAX)
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" brcs 1f \n" // {
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" subi r24, %[fract_max] \n" // f -= FRACT_MAX; millis_inc++; (++ in the form of reverse carry)
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"1: \n" // }
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" sts %[fract], r24 \n" // timer0_fract = f;
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// timer0_millis += millis_inc (addition by substracting negative value)
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" ldi r30, lo8(%[millis]) \n"
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" ldi r31, hi8(%[millis]) \n"
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" ld r24, z \n"
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" sbci r24, -%[millis_inc] - 1 \n" // r24 -= 0 - MILLIS_INC - 1 + (f >= FRACT_MAX ? 0 : 1)
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" st z, r24 \n"
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" ldd r25, z+1 \n"
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" sbci r25, 0xFF \n" // save (uint8_t)(timer0_millis >> 8) in 25
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" std z+1, r25 \n"
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" ldd r24, z+2 \n"
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" sbci r24, 0xFF \n"
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" std z+2, r24 \n"
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" ldd r24, z+3 \n"
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" sbci r24, 0xFF \n"
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" std z+3, r24 \n"
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// timer0_overflow_count++;
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" ldi r30, lo8(%[count]) \n"
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" ldi r31, hi8(%[count]) \n"
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" ld r24, z \n"
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" subi r24, 0xFF \n" // ++ (addition by substracting negative value)
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" st z, r24 \n"
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" ldd r24, z+1 \n"
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" sbci r24, 0xFF \n"
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" std z+1, r24 \n"
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" ldd r24, z+2 \n"
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" sbci r24, 0xFF \n"
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" std z+2, r24 \n"
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" ldd r24, z+3 \n"
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" sbci r24, 0xFF \n"
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" std z+3, r24 \n"
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//read Arduboy buttons
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#ifdef AB_DEVKIT
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" in r24, %[pinb] \n" // down, left, up buttons
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" ori r24, 0x8F \n"
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" sbis %[pinc], 6 \n" // skip right button not pressed
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" andi r24, 0xFB \n"
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" sbic %[pinf], 7 \n" // skip A button pressed
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" sbis %[pinf], 6 \n" // skip B button not pressed
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" clr r24 \n"
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" cpi r24, 0xAF \n" // test DevKit UP+DOWN for bootloader
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#else
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" in r24, %[pinf] \n" // directional buttons
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" ori r24, 0x0F \n" // ignore unon button bits
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" sbic %[pine], 6 \n" // skip A button pressed
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" sbis %[pinb], 4 \n" // skip B button not pressed
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" clr r24 \n" // A or B is pressed here, make compare fail
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" cpi r24, 0x6F \n" // test arduboy UP+DOWN only for bootloader
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#endif
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" brne 5f \n" // skip button combo not pressed
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// test button combo hold long enough
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"2: lds r24, %[hold] \n"
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" sub r25, r24 \n" // (uint8_t)(timer0_millis >> 8) - button_ticks_hold
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" cpi r25, 6 \n" // 1536ms >> 8
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" brcs 6f \n" // skip not long enough
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//button combo pressed long enough: trigger bootloader mode
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".global exit_to_bootloader \n"
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"exit_to_bootloader: \n"
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" ldi r30, 0x00 \n" //MAGIC KEY address (r30 is 0 from above)
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" ldi r31, 0x08 \n"
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" ldi r24, 0x77 \n" //MAGIC KEY
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" st Z, r24 \n"
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" std Z+1, r24 \n"
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" ldi r24, %[value1] \n" // set watchdog timer
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" ; ldi r31, %[value2] \n"
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" sts %[wdtcsr], r24 \n"
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" sts %[wdtcsr], r31 \n" //r31 == 08 == _BV(WDE)
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" rjmp .-2 \n" // infinite loop will trigger watchdog reset
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"5: \n" // }
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// reset button_ticks_hold
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" sts %[hold], r25 \n" // button_ticks_hold = (uint8_t)(Millis >> 8)
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"6: \n"
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//restore registers and return from interrupt
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" pop r31 \n"
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" pop r30 \n"
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" pop r25 \n"
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" pop r24 \n"
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" out __SREG__, r0 \n"
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" pop r0 \n"
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" reti \n"
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:
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: [millis] "" (&timer0_millis),
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[fract] "" (&timer0_fract),
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[millis_inc] "M" (MILLIS_INC),
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[fract_inc] "M" (FRACT_INC),
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[fract_max] "M" (FRACT_MAX),
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[count] "" (&timer0_overflow_count),
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[hold] "" (&button_ticks_hold),
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[pinf] "I" (_SFR_IO_ADDR(PINF)),
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[pine] "I" (_SFR_IO_ADDR(PINE)),
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[pinc] "I" (_SFR_IO_ADDR(PINC)),
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[pinb] "I" (_SFR_IO_ADDR(PINB)),
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[value1] "M" ((uint8_t)(_BV(WDCE) | _BV(WDE))),
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[value2] "M" ((uint8_t)(_BV(WDE))),
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[wdtcsr] "M" (_SFR_MEM_ADDR(WDTCSR))
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:
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);
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}
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unsigned long millis()
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{
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unsigned long m;
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uint8_t oldSREG = SREG;
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// disable interrupts while we read timer0_millis or we might get an
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// inconsistent value (e.g. in the middle of a write to timer0_millis)
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cli();
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m = timer0_millis;
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SREG = oldSREG;
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return m;
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}
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unsigned long micros() {
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/*
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unsigned long m;
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uint8_t oldSREG = SREG, t;
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cli();
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m = timer0_overflow_count;
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#if defined(TCNT0)
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t = TCNT0;
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#elif defined(TCNT0L)
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t = TCNT0L;
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#else
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#error TIMER 0 not defined
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#endif
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#ifdef TIFR0
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if ((TIFR0 & _BV(TOV0)) && (t < 255))
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m++;
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#else
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if ((TIFR & _BV(TOV0)) && (t < 255))
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m++;
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#endif
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SREG = oldSREG;
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return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond());
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*/
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//assembly optimalisation
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register unsigned long m asm("r22");
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asm volatile(
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" in r18, %[sreg] \n" //oldSREG = SREG
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" cli \n" //
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" ld r23, x+ \n" // m = timer0_overflow_count << 8
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" ld r24, x+ \n"
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" ld r25, x \n"
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" in r22, %[tcnt] \n" // (m << 8) | t
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" out %[sreg], r18 \n" //SREG = oldSREG
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" sbis %[tif], %[tov] \n" // if ((TIFR & _BV(TOV) &&
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" rjmp 1f \n"
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" cpi r22, 0xFF \n" // t < 0xFF)
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" brcc 1f \n"
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" \n"
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" subi r23, 0xFF \n" // m++ (m+=256)
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" sbci r24, 0xFF \n" //
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" sbci r25, 0xFF \n" //
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"1: \n"
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" ldi r18,%[fm] \n" // *( 64 / clockCyclesPerMicrosecond()
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"2: \n"
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" add r22, r22 \n"
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" adc r23, r23 \n"
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" adc r24, r24 \n"
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" adc r25, r25 \n"
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" dec r18 \n"
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" brne 2b \n"
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: "=d" (m)
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: [sreg] "I" (_SFR_IO_ADDR(SREG)),
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#if defined(TCNT0)
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[tcnt] "I" (_SFR_IO_ADDR(TCNT0)),
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#elif defined(TCNT0L)
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[tcnt] "I" (_SFR_IO_ADDR(TCNT0L)),
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#else
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#error TIMER 0 not defined
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#endif
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#ifdef TIFR0
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[tif] "I" (_SFR_IO_ADDR(TIFR0)),
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#else
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[tif] "I" (_SFR_IO_ADDR(TIFR)),
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#endif
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[tov] "M" (TOV0),
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#if (F_CPU == 8000000L)
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[fm] "M" (4),
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#elif (F_CPU ==16000000L)
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[fm] "M" (2),
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#else
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#error this version of wiring.c only supports 8MHz and 16MHz CPU clock
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#endif
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"x" (&timer0_overflow_count)
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: "r18"
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);
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return m;
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}
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void delay(unsigned long ms)
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{
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/*
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uint32_t start = micros();
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while (ms > 0) {
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yield();
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while ( ms > 0 && (micros() - start) >= 1000) {
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ms--;
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start += 1000;
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}
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}
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*/
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//assembly optimalisation
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asm volatile(
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" movw r20, %A0 \n" //ms
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" movw r30, %C0 \n"
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" call micros \n" //endMicros = micros()
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"1: \n"
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" subi r20, 1 \n" //while (ms > 0)
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" sbc r21, r1 \n"
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" sbc r30, r1 \n"
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" sbc r31, r1 \n"
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" brcs 2f \n"
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" \n"
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" subi r22, 0x18 \n" //endMicros += 1000
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" sbci r23, 0xFC \n"
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" sbci r24, 0xFF \n"
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" sbci r25, 0xFF \n"
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" rjmp 1b \n"
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"2: \n"
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" movw r20, r22 \n"
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" movw r30, r24 \n"
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"3: \n"
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" call micros \n" //while (micros() < endMicros);
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" cp r22, r20 \n"
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" cpc r23, r21 \n"
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" cpc r24, r30 \n"
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" cpc r25, r31 \n"
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" brcs 3b \n"
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:
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: "d" (ms),
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"" (micros)
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: "r20", "r21", "r30", "r31", /*from micros: */ "r18", "r26", "r27"
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);
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}
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void delayShort(unsigned short ms)
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{
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asm volatile(
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" call micros \n" //endMicros = micros()
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"1: \n"
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" sbiw r30, 1 \n" //while (ms > 0)
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" brcs 2f \n"
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" \n"
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" subi r22, 0x18 \n" //endMicros += 1000
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" sbci r23, 0xFC \n"
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" sbci r24, 0xFF \n"
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" sbci r25, 0xFF \n"
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" rjmp 1b \n"
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"2: \n"
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" movw r20, r22 \n"
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" movw r30, r24 \n"
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"3: \n"
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" call micros \n" //while (micros() < endMicros);
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" cp r22, r20 \n"
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" cpc r23, r21 \n"
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" cpc r24, r30 \n"
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" cpc r25, r31 \n"
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" brcs 3b \n"
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:
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: "z" (ms),
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"" (micros)
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: "r20", "r21", "r22", "r23", /*from micros: */ "r18", "r26", "r27"
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);
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}
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/* Delay for the given number of microseconds. Assumes a 1, 8, 12, 16, 20 or 24 MHz clock. */
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void delayMicroseconds(unsigned int us)
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{
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// call = 4 cycles + 2 to 4 cycles to init us(2 for constant delay, 4 for variable)
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// calling avrlib's delay_us() function with low values (e.g. 1 or
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// 2 microseconds) gives delays longer than desired.
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//delay_us(us);
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#if F_CPU >= 24000000L
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// for the 24 MHz clock for the aventurous ones, trying to overclock
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// zero delay fix
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if (!us) return; // = 3 cycles, (4 when true)
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// the following loop takes a 1/6 of a microsecond (4 cycles)
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// per iteration, so execute it six times for each microsecond of
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// delay requested.
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us *= 6; // x6 us, = 7 cycles
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// account for the time taken in the preceeding commands.
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// we just burned 22 (24) cycles above, remove 5, (5*4=20)
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// us is at least 6 so we can substract 5
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us -= 5; //=2 cycles
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#elif F_CPU >= 20000000L
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// for the 20 MHz clock on rare Arduino boards
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// for a one-microsecond delay, simply return. the overhead
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// of the function call takes 18 (20) cycles, which is 1us
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__asm__ __volatile__ (
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"nop" "\n"
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"nop" "\n"
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"nop" "\n"
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"nop"); //just waiting 4 cycles
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if (us <= 1) return; // = 3 cycles, (4 when true)
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// the following loop takes a 1/5 of a microsecond (4 cycles)
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// per iteration, so execute it five times for each microsecond of
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// delay requested.
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us = (us << 2) + us; // x5 us, = 7 cycles
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// account for the time taken in the preceeding commands.
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// we just burned 26 (28) cycles above, remove 7, (7*4=28)
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// us is at least 10 so we can substract 7
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us -= 7; // 2 cycles
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#elif F_CPU >= 16000000L
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// for the 16 MHz clock on most Arduino boards
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// for a one-microsecond delay, simply return. the overhead
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// of the function call takes 14 (16) cycles, which is 1us
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if (us <= 1) return; // = 3 cycles, (4 when true)
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// the following loop takes 1/4 of a microsecond (4 cycles)
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// per iteration, so execute it four times for each microsecond of
|
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// delay requested.
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us <<= 2; // x4 us, = 4 cycles
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// account for the time taken in the preceeding commands.
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// we just burned 19 (21) cycles above, remove 5, (5*4=20)
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// us is at least 8 so we can substract 5
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us -= 5; // = 2 cycles,
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#elif F_CPU >= 12000000L
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// for the 12 MHz clock if somebody is working with USB
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// for a 1 microsecond delay, simply return. the overhead
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// of the function call takes 14 (16) cycles, which is 1.5us
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if (us <= 1) return; // = 3 cycles, (4 when true)
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// the following loop takes 1/3 of a microsecond (4 cycles)
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// per iteration, so execute it three times for each microsecond of
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// delay requested.
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us = (us << 1) + us; // x3 us, = 5 cycles
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// account for the time taken in the preceeding commands.
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// we just burned 20 (22) cycles above, remove 5, (5*4=20)
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// us is at least 6 so we can substract 5
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us -= 5; //2 cycles
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#elif F_CPU >= 8000000L
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// for the 8 MHz internal clock
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// for a 1 and 2 microsecond delay, simply return. the overhead
|
|
// of the function call takes 14 (16) cycles, which is 2us
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if (us <= 2) return; // = 3 cycles, (4 when true)
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|
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// the following loop takes 1/2 of a microsecond (4 cycles)
|
|
// per iteration, so execute it twice for each microsecond of
|
|
// delay requested.
|
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us <<= 1; //x2 us, = 2 cycles
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// account for the time taken in the preceeding commands.
|
|
// we just burned 17 (19) cycles above, remove 4, (4*4=16)
|
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// us is at least 6 so we can substract 4
|
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us -= 4; // = 2 cycles
|
|
|
|
#else
|
|
// for the 1 MHz internal clock (default settings for common Atmega microcontrollers)
|
|
|
|
// the overhead of the function calls is 14 (16) cycles
|
|
if (us <= 16) return; //= 3 cycles, (4 when true)
|
|
if (us <= 25) return; //= 3 cycles, (4 when true), (must be at least 25 if we want to substract 22)
|
|
|
|
// compensate for the time taken by the preceeding and next commands (about 22 cycles)
|
|
us -= 22; // = 2 cycles
|
|
// the following loop takes 4 microseconds (4 cycles)
|
|
// per iteration, so execute it us/4 times
|
|
// us is at least 4, divided by 4 gives us 1 (no zero delay bug)
|
|
us >>= 2; // us div 4, = 4 cycles
|
|
|
|
|
|
#endif
|
|
|
|
// busy wait
|
|
__asm__ __volatile__ (
|
|
"1: sbiw %0,1" "\n" // 2 cycles
|
|
"brne 1b" : "=w" (us) : "0" (us) // 2 cycles
|
|
);
|
|
// return = 4 cycles
|
|
}
|
|
|
|
void init() //assembly optimized by 68 bytes
|
|
{
|
|
// this needs to be called before setup() or some functions won't
|
|
// work there
|
|
sei();
|
|
|
|
// on the ATmega168, timer 0 is also used for fast hardware pwm
|
|
// (using phase-correct PWM would mean that timer 0 overflowed half as often
|
|
// resulting in different millis() behavior on the ATmega8 and ATmega168)
|
|
#if defined(TCCR0A) && defined(WGM01)
|
|
//sbi(TCCR0A, WGM01);
|
|
//sbi(TCCR0A, WGM00);
|
|
asm volatile(
|
|
" ldi r24, %[value] \n"
|
|
" out %[tccr0a], r24 \n"
|
|
:
|
|
: [tccr0a] "I" (_SFR_IO_ADDR(TCCR0A)),
|
|
[value] "M" (_BV(WGM01) | _BV(WGM00))
|
|
: "r24"
|
|
);
|
|
#endif
|
|
|
|
// set timer 0 prescale factor to 64
|
|
#if defined(__AVR_ATmega128__)
|
|
// CPU specific: different values for the ATmega128
|
|
sbi(TCCR0, CS02);
|
|
#elif defined(TCCR0) && defined(CS01) && defined(CS00)
|
|
// this combination is for the standard atmega8
|
|
sbi(TCCR0, CS01);
|
|
sbi(TCCR0, CS00);
|
|
#elif defined(TCCR0B) && defined(CS01) && defined(CS00)
|
|
// this combination is for the standard 168/328/1280/2560
|
|
//sbi(TCCR0B, CS01);
|
|
//sbi(TCCR0B, CS00);
|
|
asm volatile(
|
|
" ldi r24, %[value] \n"
|
|
" out %[tccr0b], r24 \n"
|
|
:
|
|
: [tccr0b] "I" (_SFR_IO_ADDR(TCCR0B)),
|
|
[value] "M" (_BV(CS01) | _BV(CS00))
|
|
: "r24"
|
|
);
|
|
#elif defined(TCCR0A) && defined(CS01) && defined(CS00)
|
|
// this combination is for the __AVR_ATmega645__ series
|
|
sbi(TCCR0A, CS01);
|
|
sbi(TCCR0A, CS00);
|
|
#else
|
|
#error Timer 0 prescale factor 64 not set correctly
|
|
#endif
|
|
|
|
// enable timer 0 overflow interrupt
|
|
#if defined(TIMSK) && defined(TOIE0)
|
|
sbi(TIMSK, TOIE0);
|
|
#elif defined(TIMSK0) && defined(TOIE0)
|
|
TIMSK0 = _BV(TOIE0);
|
|
#else
|
|
#error Timer 0 overflow interrupt not set correctly
|
|
#endif
|
|
|
|
// timers 1 and 2 are used for phase-correct hardware pwm
|
|
// this is better for motors as it ensures an even waveform
|
|
// note, however, that fast pwm mode can achieve a frequency of up
|
|
// 8 MHz (with a 16 MHz clock) at 50% duty cycle
|
|
|
|
#if defined(TCCR1B) && defined(CS11) && defined(CS10)
|
|
//TCCR1B = 0;
|
|
|
|
// set timer 1 prescale factor to 64
|
|
//sbi(TCCR1B, CS11);
|
|
//#if F_CPU >= 8000000L
|
|
//sbi(TCCR1B, CS10);
|
|
//#endif
|
|
asm volatile(
|
|
" ldi r30, %[tccr1b] \n"
|
|
" ldi r31, 0x00 \n"
|
|
" ldi r24, %[value] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr1b] "M" (_SFR_MEM_ADDR(TCCR1B)),
|
|
#if F_CPU >= 8000000L
|
|
[value] "M" (_BV(CS11) | _BV(CS10))
|
|
#else
|
|
[value] "M" (_BV(CS11))
|
|
#endif
|
|
: "r24", "r30", "r31"
|
|
);
|
|
|
|
#elif defined(TCCR1) && defined(CS11) && defined(CS10)
|
|
sbi(TCCR1, CS11);
|
|
#if F_CPU >= 8000000L
|
|
sbi(TCCR1, CS10);
|
|
#endif
|
|
#endif
|
|
// put timer 1 in 8-bit phase correct pwm mode
|
|
#if defined(TCCR1A) && defined(WGM10)
|
|
//sbi(TCCR1A, WGM10);
|
|
asm volatile(
|
|
" ldi r30, %[tccr1a] \n"
|
|
" ldi r24, %[wgm10] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr1a] "M" (_SFR_MEM_ADDR(TCCR1A)),
|
|
[wgm10] "M" (_BV(WGM10))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
#endif
|
|
|
|
// set timer 2 prescale factor to 64
|
|
#if defined(TCCR2) && defined(CS22)
|
|
sbi(TCCR2, CS22);
|
|
#elif defined(TCCR2B) && defined(CS22)
|
|
sbi(TCCR2B, CS22);
|
|
//#else
|
|
// Timer 2 not finished (may not be present on this CPU)
|
|
#endif
|
|
|
|
// configure timer 2 for phase correct pwm (8-bit)
|
|
#if defined(TCCR2) && defined(WGM20)
|
|
sbi(TCCR2, WGM20);
|
|
#elif defined(TCCR2A) && defined(WGM20)
|
|
sbi(TCCR2A, WGM20);
|
|
//#else
|
|
// Timer 2 not finished (may not be present on this CPU)
|
|
#endif
|
|
|
|
#if defined(TCCR3B) && defined(CS31) && defined(WGM30)
|
|
//sbi(TCCR3B, CS31); // set timer 3 prescale factor to 64
|
|
//sbi(TCCR3B, CS30);
|
|
asm volatile(
|
|
" ldi r30, %[tccr3b] \n"
|
|
" ldi r24, %[value] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr3b] "M" (_SFR_MEM_ADDR(TCCR3B)),
|
|
[value] "M" (_BV(CS31) | _BV(CS30))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
//sbi(TCCR3A, WGM30); // put timer 3 in 8-bit phase correct pwm mode
|
|
asm volatile(
|
|
" ldi r30, %[tccr3a] \n"
|
|
" ldi r24, %[wgm30] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr3a] "M" (_SFR_MEM_ADDR(TCCR3A)),
|
|
[wgm30] "M" (_BV(WGM30))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
#endif
|
|
|
|
#if defined(TCCR4A) && defined(TCCR4B) && defined(TCCR4D) /* beginning of timer4 block for 32U4 and similar */
|
|
//sbi(TCCR4B, CS42); // set timer4 prescale factor to 64
|
|
//sbi(TCCR4B, CS41);
|
|
//sbi(TCCR4B, CS40);
|
|
asm volatile(
|
|
" ldi r30, %[tccr4b] \n"
|
|
" ldi r24, %[value] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr4b] "M" (_SFR_MEM_ADDR(TCCR4B)),
|
|
[value] "M" (_BV(CS42) | _BV(CS41) | _BV(CS40))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
//sbi(TCCR4D, WGM40); // put timer 4 in phase- and frequency-correct PWM mode
|
|
asm volatile(
|
|
" ldi r30, %[tccr4d] \n"
|
|
" ldi r24, %[wgm40] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr4d] "M" (_SFR_MEM_ADDR(TCCR4D)),
|
|
[wgm40] "M" (_BV(WGM40))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
//sbi(TCCR4A, PWM4A); // enable PWM mode for comparator OCR4A
|
|
asm volatile(
|
|
" ldi r30, %[tccr4a] \n"
|
|
" ldi r24, %[pwm4a] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr4a] "M" (_SFR_MEM_ADDR(TCCR4A)),
|
|
[pwm4a] "M" (_BV(PWM4A))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
//sbi(TCCR4C, PWM4D); // enable PWM mode for comparator OCR4D
|
|
asm volatile(
|
|
" ldi r30, %[tccr4c] \n"
|
|
" ldi r24, %[value] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [tccr4c] "M" (_SFR_MEM_ADDR(TCCR4C)),
|
|
[value] "M" (_BV(PWM4D))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
#else /* beginning of timer4 block for ATMEGA1280 and ATMEGA2560 */
|
|
#if defined(TCCR4B) && defined(CS41) && defined(WGM40)
|
|
sbi(TCCR4B, CS41); // set timer 4 prescale factor to 64
|
|
sbi(TCCR4B, CS40);
|
|
sbi(TCCR4A, WGM40); // put timer 4 in 8-bit phase correct pwm mode
|
|
#endif
|
|
#endif /* end timer4 block for ATMEGA1280/2560 and similar */
|
|
|
|
#if defined(TCCR5B) && defined(CS51) && defined(WGM50)
|
|
sbi(TCCR5B, CS51); // set timer 5 prescale factor to 64
|
|
sbi(TCCR5B, CS50);
|
|
sbi(TCCR5A, WGM50); // put timer 5 in 8-bit phase correct pwm mode
|
|
#endif
|
|
|
|
#if defined(ADCSRA)
|
|
// set a2d prescaler so we are inside the desired 50-200 KHz range.
|
|
#if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz
|
|
//sbi(ADCSRA, ADPS2);
|
|
//sbi(ADCSRA, ADPS1);
|
|
//sbi(ADCSRA, ADPS0);
|
|
asm volatile(
|
|
" ldi r30, %[adcsra] \n"
|
|
" ldi r24, %[value] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [adcsra] "M" (_SFR_MEM_ADDR(ADCSRA)),
|
|
[value] "M" (_BV(ADPS2) |_BV(ADPS1) | _BV(ADPS0))
|
|
: "r24"
|
|
);
|
|
#elif F_CPU >= 8000000 // 8 MHz / 64 = 125 KHz
|
|
//sbi(ADCSRA, ADPS2);
|
|
//sbi(ADCSRA, ADPS1);
|
|
//cbi(ADCSRA, ADPS0);
|
|
asm volatile(
|
|
" ldi r30, %[adcsra] \n"
|
|
" ldi r24, %[value] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [adcsra] "M" (_SFR_MEM_ADDR(ADCSRA)),
|
|
[value] "M" (_BV(ADPS2) | _BV(ADPS1))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
#elif F_CPU >= 4000000 // 4 MHz / 32 = 125 KHz
|
|
sbi(ADCSRA, ADPS2);
|
|
cbi(ADCSRA, ADPS1);
|
|
sbi(ADCSRA, ADPS0);
|
|
#elif F_CPU >= 2000000 // 2 MHz / 16 = 125 KHz
|
|
sbi(ADCSRA, ADPS2);
|
|
cbi(ADCSRA, ADPS1);
|
|
cbi(ADCSRA, ADPS0);
|
|
#elif F_CPU >= 1000000 // 1 MHz / 8 = 125 KHz
|
|
cbi(ADCSRA, ADPS2);
|
|
sbi(ADCSRA, ADPS1);
|
|
sbi(ADCSRA, ADPS0);
|
|
#else // 128 kHz / 2 = 64 KHz -> This is the closest you can get, the prescaler is 2
|
|
cbi(ADCSRA, ADPS2);
|
|
cbi(ADCSRA, ADPS1);
|
|
sbi(ADCSRA, ADPS0);
|
|
#endif
|
|
// enable a2d conversions
|
|
//sbi(ADCSRA, ADEN);
|
|
asm volatile(
|
|
" ori r24, %[aden] \n"
|
|
" st z, r24 \n"
|
|
:
|
|
: [aden] "M" (_BV(ADEN))
|
|
: "r24", "r30", "r31"
|
|
);
|
|
#endif
|
|
//(below not relevant for atmega32u4)
|
|
// the bootloader connects pins 0 and 1 to the USART; disconnect them
|
|
// here so they can be used as normal digital i/o; they will be
|
|
// reconnected in Serial.begin()
|
|
#if defined(UCSRB)
|
|
UCSRB = 0;
|
|
#elif defined(UCSR0B)
|
|
UCSR0B = 0;
|
|
#endif
|
|
} |