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MD3x0: update radio driver

This commit is contained in:
Silvano Seva 2024-07-19 22:05:01 +02:00
parent c34e4462c2
commit 0c4a0435a8
5 changed files with 47 additions and 14 deletions
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4
meson.build
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@ -161,7 +161,9 @@ mdx_src = ['platform/drivers/ADC/ADC1_MDx.c',
'platform/drivers/NVM/nvmem_MDx.c', 'platform/drivers/NVM/nvmem_MDx.c',
'platform/drivers/audio/audio_MDx.c', 'platform/drivers/audio/audio_MDx.c',
'platform/drivers/baseband/HR_Cx000.cpp', 'platform/drivers/baseband/HR_Cx000.cpp',
'platform/drivers/tones/toneGenerator_MDx.cpp'] 'platform/drivers/tones/toneGenerator_MDx.cpp',
'platform/drivers/SPI/spi_custom.c',
'platform/drivers/SPI/spi_bitbang.c']
## ##
## GDx family: Radioddity GD-77 and Baofeng DM-1801 ## GDx family: Radioddity GD-77 and Baofeng DM-1801

22
platform/drivers/baseband/radio_MD3x0.cpp
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@ -1,5 +1,5 @@
/*************************************************************************** /***************************************************************************
* Copyright (C) 2021 - 2023 by Federico Amedeo Izzo IU2NUO, * * Copyright (C) 2021 - 2024 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN * * Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO * * Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO * * Silvano Seva IU2KWO *
@ -23,6 +23,7 @@
#include <interfaces/radio.h> #include <interfaces/radio.h>
#include <peripherals/gpio.h> #include <peripherals/gpio.h>
#include <calibInfo_MDx.h> #include <calibInfo_MDx.h>
#include <spi_bitbang.h>
#include <hwconfig.h> #include <hwconfig.h>
#include <ADC1_MDx.h> #include <ADC1_MDx.h>
#include <algorithm> #include <algorithm>
@ -42,7 +43,7 @@ static uint8_t txpwr_hi = 0; // APC voltage for TX output pow
static enum opstatus radioStatus; // Current operating status static enum opstatus radioStatus; // Current operating status
static HR_C5000& C5000 = HR_C5000::instance(); // HR_C5000 driver static HR_C5000 C5000((const struct spiDevice *) &c5000_spi, { DMR_CS });
/* /*
* Parameters for RSSI voltage (mV) to input power (dBm) conversion. * Parameters for RSSI voltage (mV) to input power (dBm) conversion.
@ -128,14 +129,13 @@ void radio_init(const rtxStatus_t *rtxState)
nvm_readCalibData(&calData); nvm_readCalibData(&calData);
/* /*
* Enable and configure PLL * Enable and configure PLL and HR_C5000
*/ */
gpio_setPin(PLL_PWR); spiBitbang_init(&pll_spi);
SKY73210_init(); spiBitbang_init(&c5000_spi);
/* gpio_setPin(PLL_PWR);
* Configure HR_C5000 SKY73210_init(&pll);
*/
C5000.init(); C5000.init();
/* /*
@ -147,7 +147,7 @@ void radio_init(const rtxStatus_t *rtxState)
void radio_terminate() void radio_terminate()
{ {
SKY73210_terminate(); SKY73210_terminate(&pll);
C5000.terminate(); C5000.terminate();
gpio_clearPin(PLL_PWR); // PLL off gpio_clearPin(PLL_PWR); // PLL off
@ -251,7 +251,7 @@ void radio_enableRx()
pllFreq -= static_cast< float >(IF_FREQ); pllFreq -= static_cast< float >(IF_FREQ);
} }
SKY73210_setFrequency(pllFreq, 5); SKY73210_setFrequency(&pll, pllFreq, 5);
DAC->DHR12L1 = vtune_rx * 0xFF; DAC->DHR12L1 = vtune_rx * 0xFF;
gpio_setPin(RX_STG_EN); // Enable RX LNA gpio_setPin(RX_STG_EN); // Enable RX LNA
@ -270,7 +270,7 @@ void radio_enableTx()
// Set PLL frequency. // Set PLL frequency.
float pllFreq = static_cast< float >(config->txFrequency); float pllFreq = static_cast< float >(config->txFrequency);
if(isVhfBand) pllFreq *= 2.0f; if(isVhfBand) pllFreq *= 2.0f;
SKY73210_setFrequency(pllFreq, 5); SKY73210_setFrequency(&pll, pllFreq, 5);
// Set TX output power, constrain between 1W and 5W. // Set TX output power, constrain between 1W and 5W.
float power = static_cast < float >(config->txPower) / 1000.0f; float power = static_cast < float >(config->txPower) / 1000.0f;

28
platform/targets/MD-3x0/hwconfig.c
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@ -21,7 +21,35 @@
#include <spi_bitbang.h> #include <spi_bitbang.h>
#include <spi_custom.h> #include <spi_custom.h>
#include <spi_stm32.h> #include <spi_stm32.h>
#include <SKY72310.h>
#include <hwconfig.h> #include <hwconfig.h>
#include <pinmap.h> #include <pinmap.h>
const struct spiConfig spiPllCfg =
{
.clk = { PLL_CLK },
.mosi = { PLL_DAT },
.miso = { PLL_DAT },
.clkPeriod = SCK_PERIOD_FROM_FREQ(1000000),
.flags = SPI_HALF_DUPLEX
};
const struct spiConfig spiC5000Cfg =
{
.clk = { DMR_CLK },
.mosi = { DMR_MOSI },
.miso = { DMR_MISO },
.clkPeriod = SCK_PERIOD_FROM_FREQ(1000000),
.flags = SPI_FLAG_CPHA
};
SPI_STM32_DEVICE_DEFINE(nvm_spi, SPI1, NULL) SPI_STM32_DEVICE_DEFINE(nvm_spi, SPI1, NULL)
SPI_BITBANG_DEVICE_DEFINE(pll_spi, spiPllCfg, NULL)
SPI_BITBANG_DEVICE_DEFINE(c5000_spi, spiC5000Cfg, NULL)
const struct sky73210 pll =
{
.spi = (const struct spiDevice *) &pll_spi,
.cs = { PLL_CS },
.refClk = 16800000
};

3
platform/targets/MD-3x0/hwconfig.h
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@ -28,6 +28,9 @@ extern "C" {
#endif #endif
extern const struct spiDevice nvm_spi; extern const struct spiDevice nvm_spi;
extern const struct spiCustomDevice pll_spi;
extern const struct spiCustomDevice c5000_spi;
extern const struct sky73210 pll;
/* Device has a working real time clock */ /* Device has a working real time clock */
#define CONFIG_RTC #define CONFIG_RTC

4
platform/targets/MD-3x0/pinmap.h
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@ -87,13 +87,13 @@
#define FLASH_SDI GPIOB,5 #define FLASH_SDI GPIOB,5
/* PLL */ /* PLL */
#define PLL_CS GPIOD,11 #define PLL_CS &GpioD,11
#define PLL_CLK GPIOE,4 #define PLL_CLK GPIOE,4
#define PLL_DAT GPIOE,5 /* WARNING: this line is also HR_C5000 MOSI */ #define PLL_DAT GPIOE,5 /* WARNING: this line is also HR_C5000 MOSI */
#define PLL_LD GPIOD,10 #define PLL_LD GPIOD,10
/* HR_C5000 */ /* HR_C5000 */
#define DMR_CS GPIOE,2 #define DMR_CS &GpioE,2
#define DMR_CLK GPIOC,13 #define DMR_CLK GPIOC,13
#define DMR_MOSI PLL_DAT #define DMR_MOSI PLL_DAT
#define DMR_MISO GPIOE,3 #define DMR_MISO GPIOE,3