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Fixed regression affecting USB virtual COM port on TYT MD-380

This commit is contained in:
Silvano Seva 2020-11-16 11:02:31 +01:00
parent e2dd96356d
commit 76086d567f
2 changed files with 17 additions and 19 deletions
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15
platform/mcu/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c
View File

@ -249,7 +249,7 @@ void SystemCoreClockUpdate(void)
else else
{ {
/* HSI used as PLL clock source */ /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
} }
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
@ -306,18 +306,21 @@ static void SetSysClock(void)
RCC->APB1ENR |= RCC_APB1ENR_PWREN; RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS; PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/ /* HCLK = SYSCLK / 1 */
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/ /* PCLK2 = HCLK / 2 */
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/ /* PCLK1 = HCLK / 4 */
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */ /* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 5) | (((PLL_P >> 1) -1) << 16) | RCC->PLLCFGR = (PLL_Q << 24) /* PLL divider for USB clock */
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); | RCC_PLLCFGR_PLLSRC_HSE /* HSE as PLL clock source */
| (((PLL_P >> 1) -1) << 16) /* PLL divider for main clock */
| (PLL_N << 6) /* PLL multiplier */
| PLL_M; /* Input clock divider */
/* Enable the main PLL */ /* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;

21
platform/mcu/STM32F4xx/drivers/usb/usb_bsp.c
View File

@ -31,6 +31,8 @@
#include "usbd_conf.h" #include "usbd_conf.h"
#include "stm32f4xx.h" #include "stm32f4xx.h"
#include "gpio.h" #include "gpio.h"
#include <os.h>
#include <delays.h>
extern USB_OTG_CORE_HANDLE USB_OTG_dev; extern USB_OTG_CORE_HANDLE USB_OTG_dev;
extern uint32_t USBD_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev); extern uint32_t USBD_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev);
@ -78,18 +80,9 @@ void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev)
* @param usec : Value of delay required in micro sec * @param usec : Value of delay required in micro sec
* @retval None * @retval None
*/ */
void USB_OTG_BSP_uDelay (const uint32_t usec) { void USB_OTG_BSP_uDelay (const uint32_t usec)
{
uint32_t count = 0; delayUs(usec);
const uint32_t utime = (120 * usec / 7);
do
{
if( ++count > utime )
{
return ;
}
} while (1);
} }
@ -101,11 +94,13 @@ void USB_OTG_BSP_uDelay (const uint32_t usec) {
*/ */
void USB_OTG_BSP_mDelay (const uint32_t msec) void USB_OTG_BSP_mDelay (const uint32_t msec)
{ {
USB_OTG_BSP_uDelay(msec * 1000); delayMs(msec);
} }
void OTG_FS_IRQHandler(void) void OTG_FS_IRQHandler(void)
{ {
OSIntEnter();
USBD_OTG_ISR_Handler (&USB_OTG_dev); USBD_OTG_ISR_Handler (&USB_OTG_dev);
OSIntExit();
} }