306 lines
10 KiB
C++
306 lines
10 KiB
C++
/***************************************************************************
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* Copyright (C) 2021 - 2022 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <kernel/scheduler/scheduler.h>
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#include <interfaces/audio_stream.h>
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#include <interfaces/gpio.h>
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#include <data_conversion.h>
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#include <hwconfig.h>
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#include <timers.h>
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#include <miosix.h>
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static int priority = PRIO_BEEP;
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static bool running = false; // Stream is running
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static bool circularMode = false; // Circular mode enabled
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static bool reqFinish = false; // Pending termination request
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static size_t bufLen = 0; // Buffer length
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static stream_sample_t *bufAddr = 0; // Start address of data buffer, fixed.
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static stream_sample_t *idleBuf = 0;
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using namespace miosix;
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static Thread *dmaWaiting = 0;
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/**
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* \internal
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* Stop an ongoing transfer, deactivating timers and DMA stream.
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*/
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void stopTransfer()
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{
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// Stop DMA transfers
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DMA1_Stream5->CR = 0;
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DMA1_Stream6->CR = 0;
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TIM7->CR1 = 0; // Shutdown timer
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DAC->SR = 0; // Clear status flags
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DAC->CR = DAC_CR_EN1; // Keep only channel 1 active
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DAC->DHR12R1 = 2048; // Set channel 1 (RTX) to VDD/2 when idle
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// Clear flags
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running = false;
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reqFinish = false;
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circularMode = false;
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}
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/**
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* \internal
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* Actual implementation of DMA interrupt handler.
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*/
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void __attribute__((used)) DMA_Handler()
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{
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// Manage half transfer interrupt
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if((DMA1->HISR & DMA_HISR_HTIF5) || (DMA1->HISR & DMA_HISR_HTIF6))
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idleBuf = bufAddr;
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else
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idleBuf = bufAddr + (bufLen / 2);
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// Stop transfer for linear buffer mode or pending termination request.
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if((circularMode == false) || (reqFinish == true))
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{
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stopTransfer();
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}
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// Clear interrupt flags for stream 5 and 6
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uint32_t mask = DMA_HISR_TEIF5
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| DMA_HISR_TCIF5
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| DMA_HISR_HTIF5
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| DMA_HISR_TEIF6
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| DMA_HISR_TCIF6
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| DMA_HISR_HTIF6;
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DMA1->HIFCR = DMA1->HISR & mask;
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// Finally, wake up eventual pending threads
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if(dmaWaiting == 0) return;
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dmaWaiting->IRQwakeup();
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if(dmaWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority())
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Scheduler::IRQfindNextThread();
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dmaWaiting = 0;
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}
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// DMA 1, Stream 5: data transfer for RTX sink
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void __attribute__((used)) DMA1_Stream5_IRQHandler()
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{
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saveContext();
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asm volatile("bl _Z11DMA_Handlerv");
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restoreContext();
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}
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// DMA 1, Stream 6: data transfer for speaker sink
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void __attribute__((used)) DMA1_Stream6_IRQHandler()
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{
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saveContext();
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asm volatile("bl _Z11DMA_Handlerv");
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restoreContext();
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}
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streamId outputStream_start(const enum AudioSink destination,
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const enum AudioPriority prio,
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stream_sample_t * const buf,
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const size_t length,
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const enum BufMode mode,
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const uint32_t sampleRate)
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{
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// Sanity check
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if((buf == NULL) || (length == 0) || (sampleRate == 0)) return -1;
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// This device cannot sink to buffers
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if(destination == SINK_MCU) return -1;
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// Check if an output stream is already opened and, in case, handle priority.
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if(running)
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{
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if(prio < priority) return -1; // Lower priority, reject.
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if(prio > priority) stopTransfer(); // Higher priority, takes over.
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while(running) ; // Same priority, wait.
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}
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// Thread-safe block: assign priority, set stream as running and lock "beeps"
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__disable_irq();
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priority = prio;
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running = true;
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__enable_irq();
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/*
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* Convert buffer elements from int16_t to unsigned 8 bit values, as
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* required by tone generator. Processing can be done in-place because the
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* API mandates that the function caller does not modify the buffer content
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* once this function has been called.
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*/
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S16toU12(buf, length);
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bufAddr = buf;
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bufLen = length;
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idleBuf = bufAddr + (bufLen / 2);
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// Configure GPIOs
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gpio_setMode(BASEBAND_TX, INPUT_ANALOG); /* Baseband TX */
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gpio_setMode(AUDIO_SPK, INPUT_ANALOG); /* Spk output */
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/*
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* Enable peripherals
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*/
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
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RCC->APB1ENR |= RCC_APB1ENR_DACEN
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| RCC_APB1ENR_TIM7EN;
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__DSB();
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/*
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* Configure DAC and DMA stream
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*/
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uint32_t circular = 0;
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if(mode == BUF_CIRC_DOUBLE)
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{
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circular = DMA_SxCR_CIRC // Circular buffer mode
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| DMA_SxCR_HTIE; // Half transfer interrupt
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circularMode = true;
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}
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if(destination == SINK_RTX)
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{
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DAC->CR = DAC_CR_DMAEN1 // Enable DMA mode
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| DAC_CR_TSEL1_1 // TIM7 TRGO as trigger source
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| DAC_CR_TEN1 // Enable trigger input
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| DAC_CR_EN1; // Enable DAC
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DMA1_Stream5->NDTR = length;
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DMA1_Stream5->PAR = reinterpret_cast< uint32_t >(&(DAC->DHR12R1));
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DMA1_Stream5->M0AR = reinterpret_cast< uint32_t >(buf);
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DMA1_Stream5->CR = DMA_SxCR_CHSEL // Channel 7
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| DMA_SxCR_PL // Very high priority
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| DMA_SxCR_MSIZE_0 // 16 bit source size
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| DMA_SxCR_PSIZE_0 // 16 bit destination size
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| DMA_SxCR_MINC // Increment source pointer
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| DMA_SxCR_TCIE // Transfer complete interrupt
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| DMA_SxCR_TEIE // Transfer error interrupt
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| DMA_SxCR_DIR_0 // Memory to peripheral
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| circular // Circular mode
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| DMA_SxCR_EN; // Start transfer
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NVIC_ClearPendingIRQ(DMA1_Stream5_IRQn);
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NVIC_SetPriority(DMA1_Stream5_IRQn, 10);
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NVIC_EnableIRQ(DMA1_Stream5_IRQn);
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}
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else
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{
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DAC->CR = DAC_CR_DMAEN2 // Enable DMA mode
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| DAC_CR_TSEL2_1 // TIM7 TRGO as trigger source
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| DAC_CR_TEN2 // Enable trigger input
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| DAC_CR_EN2; // Enable DAC
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DMA1_Stream6->NDTR = length;
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DMA1_Stream6->PAR = reinterpret_cast< uint32_t >(&(DAC->DHR12R2));
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DMA1_Stream6->M0AR = reinterpret_cast< uint32_t >(buf);
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DMA1_Stream6->CR = DMA_SxCR_CHSEL // Channel 7
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| DMA_SxCR_PL // Very high priority
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| DMA_SxCR_MSIZE_0 // 16 bit source size
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| DMA_SxCR_PSIZE_0 // 16 bit destination size
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| DMA_SxCR_MINC // Increment source pointer
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| DMA_SxCR_TCIE // Transfer complete interrupt
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| DMA_SxCR_TEIE // Transfer error interrupt
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| DMA_SxCR_DIR_0 // Memory to peripheral
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| circular // Circular mode
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| DMA_SxCR_EN; // Start transfer
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NVIC_ClearPendingIRQ(DMA1_Stream6_IRQn);
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NVIC_SetPriority(DMA1_Stream6_IRQn, 10);
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NVIC_EnableIRQ(DMA1_Stream6_IRQn);
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}
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/*
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* TIM7 for conversion triggering via TIM7_TRGO, that is counter reload.
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* APB1 frequency is 42MHz but timer runs at 84MHz, tick rate is 1MHz,
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* reload register is configured based on desired sample rate.
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*/
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tim_setUpdateFreqency(TIM7, sampleRate, 84000000);
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TIM7->CNT = 0;
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TIM7->EGR = TIM_EGR_UG;
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TIM7->CR2 = TIM_CR2_MMS_1;
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TIM7->CR1 = TIM_CR1_CEN;
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return 0;
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}
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stream_sample_t *outputStream_getIdleBuffer(const streamId id)
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{
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(void) id;
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if(!circularMode) return nullptr;
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return idleBuf;
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}
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bool outputStream_sync(const streamId id, const bool bufChanged)
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{
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(void) id;
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if(circularMode && bufChanged)
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{
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stream_sample_t *ptr = outputStream_getIdleBuffer(id);
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S16toU12(ptr, bufLen/2);
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}
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// Enter in critical section until the end of the function
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FastInterruptDisableLock dLock;
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Thread *curThread = Thread::IRQgetCurrentThread();
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if((dmaWaiting != 0) && (dmaWaiting != curThread)) return false;
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dmaWaiting = curThread;
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do
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{
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Thread::IRQwait();
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{
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// Re-enable interrupts while waiting for IRQ
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FastInterruptEnableLock eLock(dLock);
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Thread::yield();
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}
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}
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while((dmaWaiting != 0) && (running == true));
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dmaWaiting = 0;
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return true;
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}
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void outputStream_stop(const streamId id)
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{
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(void) id;
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reqFinish = true;
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}
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void outputStream_terminate(const streamId id)
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{
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(void) id;
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FastInterruptDisableLock dLock;
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stopTransfer();
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DMA1->HIFCR = DMA_HIFCR_CTEIF5
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| DMA_HIFCR_CTCIF5
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| DMA_HIFCR_CHTIF5;
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DMA1->HIFCR = DMA_HIFCR_CTEIF6
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| DMA_HIFCR_CTCIF6
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| DMA_HIFCR_CHTIF6;
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}
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